データシートサーチシステム |
|
ADC0804LCN データシート(PDF) 5 Page - NXP Semiconductors |
|
ADC0804LCN データシート(HTML) 5 Page - NXP Semiconductors |
5 / 18 page Philips Semiconductors Product data ADC0803/0804 CMOS 8-bit A/D converters 2002 Oct 17 5 AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TO FROM TEST CONDITIONS LIMITS UNIT SYMBOL PARAMETER TO FROM TEST CONDITIONS Min Typ Max UNIT Conversion time fCLK = 1 MHz1 66 73 µs fCLK Clock frequency1 0.1 1.0 3.0 MHz Clock duty cycle1 40 60 % CR Free-running conversion rate CS = 0, fCLK = 1 MHz INTR tied to WR 13690 conv/s tW(WR)L Start pulse width CS = 0 30 ns tACC Access time Output RD CS = 0, CL = 100 pF 75 100 ns t1H, t0H 3-State control Output RD CL = 10 pF, RL = 10 kΩ See 3-State test circuit 70 100 ns tW1, tR1 INTR delay INTR WD or RD 100 150 ns CIN Logic input=capacitance 5 7.5 pF COUT 3-State output capacitance 5 7.5 pF NOTE: 1. Accuracy is guaranteed at fCLK = 1 MHz. Accuracy may degrade at higher clock frequencies. FUNCTIONAL DESCRIPTION These devices operate on the Successive Approximation principle. Analog switches are closed sequentially by successive approximation logic until the input to the auto-zero comparator [VIN(+)–VIN(–) ] matches the voltage from the decoder. After all bits are tested and determined, the 8-bit binary code corresponding to the input voltage is transferred to an output latch. Conversion begins with the arrival of a pulse at the WR input if the CS input is low. On the High-to-Low transition of the signal at the WR or the CS input, the SAR is initialized, the shift register is reset, and the INTR output is set high. The A/D will remain in the reset state as long as the CS and WR inputs remain low. Conversion will start from one to eight clock periods after one or both of these inputs makes a Low-to-High transition. After the conversion is complete, the INTR pin will make a High-to-Low transition. This can be used to interrupt a processor, or otherwise signal the availability of a new conversion result. A read (RD) operation (with CS low) will clear the INTR line and enable the output latches. The device may be run in the free-running mode as described later. A conversion in progress can be interrupted by issuing another start command. Digital Control Inputs The digital control inputs (CS, WR, RD) are compatible with standard TTL logic voltage levels. The required signals at these inputs correspond to Chip Select, START Conversion, and Output Enable control signals, respectively. They are active-Low for easy interface to microprocessor and microcontroller control buses. For applications not using microprocessors, the CS input (Pin 1) can be grounded and the A/D START function is achieved by a negative-going pulse to the WR input (Pin 3). The Output Enable function is achieved by a logic low signal at the RD input (Pin 2), which may be grounded to constantly have the latest conversion present at the output. ANALOG OPERATION Analog Input Current The analog comparisons are performed by a capacitive charge summing circuit. The input capacitor is switched between VIN(+)4 and VIN(–), while reference capacitors are switched between taps on the reference voltage divider string. The net charge corresponds to the weighted difference between the input and the most recent total value set by the successive approximation register. The internal switching action causes displacement currents to flow at the analog inputs. The voltage on the on-chip capacitance is switched through the analog differential input voltage, resulting in proportional currents entering the VIN(+) input and leaving the VIN(–) input. These transient currents occur at the leading edge of the internal clock pulses. They decay rapidly so do not inherently cause errors as the on-chip comparator is strobed at the end of the clock period. Input Bypass Capacitors and Source Resistance Bypass capacitors at the input will average the charges mentioned above, causing a DC and an AC current to flow through the output resistance of the analog signal sources. This charge pumping action is worse for continuous conversions with the VIN(+) input at full scale. This current can be a few microamps, so bypass capacitors should NOT be used at the analog inputs of the VREF/2 input for high resistance sources (> 1 k Ω). If input bypass capacitors are desired for noise filtering and a high source resistance is desired to minimize capacitor size, detrimental effects of the voltage drop across the input resistance can be eliminated by adjusting the full scale with both the input resistance and the input bypass capacitor in place. This is possible because the magnitude of the input current is a precise linear function of the differential voltage. |
同様の部品番号 - ADC0804LCN |
|
同様の説明 - ADC0804LCN |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |