データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

74AC11109D データシート(PDF) 4 Page - Texas Instruments

部品番号 74AC11109D
部品情報  DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
Download  7 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI1 - Texas Instruments

74AC11109D データシート(HTML) 4 Page - Texas Instruments

  74AC11109D Datasheet HTML 1Page - Texas Instruments 74AC11109D Datasheet HTML 2Page - Texas Instruments 74AC11109D Datasheet HTML 3Page - Texas Instruments 74AC11109D Datasheet HTML 4Page - Texas Instruments 74AC11109D Datasheet HTML 5Page - Texas Instruments 74AC11109D Datasheet HTML 6Page - Texas Instruments 74AC11109D Datasheet HTML 7Page - Texas Instruments  
Zoom Inzoom in Zoom Outzoom out
 4 / 7 page
background image
54AC11109, 74AC11109
DUAL JK POSITIVEEDGETRIGGERED FLIPFLOPS
WITH CLEAR AND PRESET
SCAS450 − MARCH 1987 − REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
2−4
timing requirements, VCC = 3.3 V ± 0.3 V (see Figure 1)
TA = 25°C
54AC11109
74AC11109
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
70
0
70
0
70
MHz
tw
Pulse duration
PRE or CLR low
5
5
5
ns
tw
Pulse duration
CLK low or CLK high
7.2
7.2
7.2
ns
tsu
Setup time before CLK
Data high or low
5.5
5.5
5.5
ns
tsu
Setup time before CLK
PRE or CLR inactive
2.5
2.5
2.5
ns
th
Hold time after CLK
0
0
0
ns
timing requirements, VCC = 5 V ± 0.5 V (see Figure 1)
TA = 25°C
54AC11109
74AC11109
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
100
0
100
0
100
MHz
tw
Pulse duration
PRE or CLR low
4
4
4
ns
tw
Pulse duration
CLK low or CLK high
5
5
5
ns
tsu
Setup time, before CLK
Data high or low
4.5
4.5
2.5
ns
tsu
Setup time, before CLK
PRE or CLR inactive
2
2
2
ns
th
Hold time, after CLK
0
0
0
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25°C
54AC11109
74AC11109
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
70
100
70
70
MHz
tPLH
PRE or CLR
Q or Q
1.5
6.5
9
1.5
10.5
1.5
9.9
ns
tPHL
PRE or CLR
Q or Q
1.5
8
12.6
1.5
14.4
1.5
13.7
ns
tPLH
CLK
Q or Q
1.5
8
11.4
1.5
13.5
1.5
12.7
ns
tPHL
CLK
Q or Q
1.5
7.5
10.5
1.5
12.7
1.5
11.8
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25°C
54AC11109
74AC11109
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
100
125
100
100
MHz
tPLH
PRE or CLR
Q or Q
1.5
4.5
6.5
1.5
7.6
1.5
7.1
ns
tPHL
PRE or CLR
Q or Q
1.5
5
8.6
1.5
10.2
1.5
9.6
ns
tPLH
CLK
Q or Q
1.5
5.5
7.9
1.5
9.4
1.5
8.8
ns
tPHL
CLK
Q or Q
1.5
5
7.3
1.5
8.6
1.5
8.1
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance per gate
CL = 50 pF,
f = 1 MHz
32
pF


同様の部品番号 - 74AC11109D

メーカー部品番号データシート部品情報
logo
Texas Instruments
74AC11109D TI-74AC11109D Datasheet
89Kb / 7P
[Old version datasheet]   DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
74AC11109DR TI-74AC11109DR Datasheet
89Kb / 7P
[Old version datasheet]   DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
More results

同様の説明 - 74AC11109D

メーカー部品番号データシート部品情報
logo
Texas Instruments
CD54ACT109 TI-CD54ACT109_08 Datasheet
349Kb / 11P
[Old version datasheet]   DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN54109 TI-SN54109 Datasheet
271Kb / 7P
[Old version datasheet]   DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR
CD54ACT109 TI-CD54ACT109 Datasheet
337Kb / 10P
[Old version datasheet]   DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN54F109 TI1-SN54F109_15 Datasheet
563Kb / 15P
[Old version datasheet]   DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74HC109NSR TI1-SN74HC109NSR Datasheet
855Kb / 19P
[Old version datasheet]   DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74LS109 TI1-SN74LS109_V01 Datasheet
409Kb / 12P
[Old version datasheet]   DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR
2022
74AC11109 TI-74AC11109 Datasheet
89Kb / 7P
[Old version datasheet]   DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN54ALS109A TI1-SN54ALS109A_15 Datasheet
1Mb / 19P
[Old version datasheet]   DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN54F109 TI-SN54F109 Datasheet
109Kb / 6P
[Old version datasheet]   DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN54ALS109A TI-SN54ALS109A Datasheet
138Kb / 9P
[Old version datasheet]   DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
logo
Hitachi Semiconductor
HD74LS109A HITACHI-HD74LS109A Datasheet
68Kb / 6P
   Dual J-K Positive-edge-triggered Flip-Flops(with Preset and Clear)
More results


Html Pages

1 2 3 4 5 6 7


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com