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AD5641AKS データシート(PDF) 6 Page - Analog Devices |
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AD5641AKS データシート(HTML) 6 Page - Analog Devices |
6 / 20 page AD5641 Preliminary Technical Data Rev. PrC | Page 6 of 20 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TOP VIEW (Not to Scale) VDD GND SCLK DIN AD5641 VOUT SYNC 1 2 3 6 5 4 Figure 3. 6-Lead SC70 Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Function 1 SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the clocks that follow. The DAC is updated following the 16th clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. 2 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. 3 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 4 VDD Power Supply Input. The AD5641 can be operated from 2.7 V to 5.5 V. VDD should be decoupled to GND. 5 GND Ground Reference Point for All Circuitry on the AD5641. 6 VOUT Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation. |
同様の部品番号 - AD5641AKS |
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同様の説明 - AD5641AKS |
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