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LM10506 データシート(PDF) 8 Page - Texas Instruments |
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LM10506 データシート(HTML) 8 Page - Texas Instruments |
8 / 43 page LM10506 SNVS729F – SEPTEMBER 2011 – REVISED AUGUST 2014 www.ti.com Buck 2 Electrical Characteristics (1)(2)(3) (continued) Unless otherwise noted, VIN = 5 V where: VIN = VVIN_B1 = VVIN_B2 = VVIN_B3. Limits apply for TJ = 25°C, unless otherwise noted. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CIN Input capacitor (5) 4.7 µF Output filter capacitor 10 10 100 (5) COUT 0 mA ≤ IOUT ≤ 400 mA Output capacitor ESR (5) 20 m Ω L Output filter inductance (5) 2.2 µH 3.3 V ≤ VIN ≤ 5 V, IOUT = 400 DC line regulation (5) 0.5 %/V mA ΔVOUT DC load regulation (5) 100 mA ≤ IOUT ≤ 400 mA 0.3 %/A IFB Feedback pin input bias current VFB = 1.8 V 1.8 5(4) µA 135 RDS-ON-HS High side switch on resistance VIN = 2.6 V 260 m Ω RDS-ON-LS Low side switch on resistance 85 190(4) STARTUP Startup from shutdown, VOUT = 0V, no load, LC = Internal soft-start (turn on time) TSTART recommended circuit, using 0.1 ms (5) software enable, to VOUT = 95% of final value 7.8 Buck 3 Electrical Characteristics (1) (2) (3) Unless otherwise noted, VIN = 5 V where: VIN = VVIN_B1 = VVIN_B2 = VVIN_B3. Limits apply for TJ = 25°C, unless otherwise noted. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IQ DC bias current in VIN No Load, PFM Mode 15 50(4) µA Buck 3 enabled, switching in IPEAK Peak switching current limit 0.9(4) 1.2 1.7(4) A PWM η Efficiency peak, Buck 3 (5) IOUT = 0.3 A 90% ƒSW Switching frequency 1.75(4) 2 2.3(4) MHz CIN Input Capacitor (5) 4.7 µF Output Filter Capacitor (5) 10 10 100 COUT 0 mA ≤ IOUT ≤ 600 mA Output Capacitor ESR (5) 20 m Ω L Output Filter Inductance (5) 2.2 µH DC Line regulation (5) 3.3 V ≤ VIN ≤ 5 V, IOUT = 600 mA 0.5 %/V ΔVOUT DC Load regulation (5) 150 mA ≤ IOUT ≤ 600 mA 0.3 %/A Feedback pin input bias IFB VFB = 1.2 V 0.9 5(4) µA current 135 High Side Switch On RDS-ON-HS Resistance VIN = 2.6 V 260 m Ω Low Side Switch On RDS-ON-LS 85 190(4) Resistance STARTUP Startup from shutdown, VOUT = 0 Internal soft-start (turn on V, no load, LC = recommended TSTART 0.1 ms time) (5) circuit, using software enable, to VOUT = 95% of final value (1) All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. (2) Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics. (3) BUCK normal operation is ensured if VIN ≥ VOUT+1 V. (4) Limits apply over the entire operating junction temperature range of −40°C ≤ TA = TJ ≤ 85°C. (5) Specification ensured by design. Not tested during production. 8 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LM10506 |
同様の部品番号 - LM10506_15 |
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同様の説明 - LM10506_15 |
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