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LM10524 データシート(PDF) 5 Page - Texas Instruments

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部品番号 LM10524
部品情報  LM10524 Triple Buck Power Management Unit
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI1 - Texas Instruments

LM10524 データシート(HTML) 5 Page - Texas Instruments

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LM10524
www.ti.com
SNVS986A – AUGUST 2013 – REVISED JANUARY 2014
Table 1. 9.0 LM10524 Pin Description
Pin #
Pin Name
I/O(1) Type(2) Functional Description
A4
DEVSLP
I
D
Digital Input Control Signal for entering Device Sleep Mode. Input activates the device
sleep function in conjunction with DEVSLP_OVR1, DEVSLP_OVR2, and PowerUp_mode.
This is an active High pin with an option for an internal pullup resistor. Turns off all outputs
and internal oscillator.
E7
DEVSLP_CTRL
O
D
Indicates DevSLP signal is active but drives low when device is in SLEEP mode.
C7
DEVSLP_OVR1
I
D
Used to gate activation of device sleep.
D7
DEVSLP_OVR2
I
D
Used to gate activation of device sleep.
C5
FB_B1
I/O
A
Buck Switcher Regulator 1 - Voltage output feedback plus Bypass Power.
B4
FB_B1
I/O
A
Buck Switcher Regulator 1 - Voltage output feedback plus Bypass Power.
C4
FB_B1
I/O
A
Buck Switcher Regulator 1 - Voltage output feedback plus Bypass Power.
F3
FB_B2
I
A
Buck Switcher Regulator 2 - Voltage output feedback.
F5
FB_B3
I
A
Buck Switcher Regulator 3 - Voltage output feedback.
C6
FREE
Not Used.
F4
FREE
Not Used.
G4
FREE
Not Used.
B1
GND
G
G
Ground. Connect to system Ground.
B2
GND
G
G
Ground. Connect to system Ground.
C2
GND
G
G
Ground. Connect to system Ground.
A7
GND_B1
G
P
Buck Switcher Regulator 1 - Power ground for Buck Regulator.
B7
GND_B1
G
P
Buck Switcher Regulator 1 - Power ground for Buck Regulator.
G1
GND_B2
G
P
Buck Switcher Regulator 2 - Power ground for Buck Regulator.
H1
GND_B2
G
P
Buck Switcher Regulator 2 - Power ground for Buck Regulator.
G7
GND_B3
G
P
Buck Switcher Regulator 3 - Power ground for Buck Regulator.
H7
GND_B3
G
P
Buck Switcher Regulator 3 - Power ground for Buck Regulator.
C3
IRQ
O
D
Interrupt. Digital Output of Comparator to signal interrupt condition.
A2
PWR_OK
O
D
PWR_OK Signal, Push Pull output.
H4
POWERUP
I/O
D
Used to indicate SSD initialization is complete. Once initialization is complete, this pin
_MODE
should be externally pulled low to allow Sleep mode activation via DEVSLP
F7
SLEEP_EN
O
D
Active high output indicates device is in Sleep Mode.
C1
SPI_CLK
I
D
SPI Interface - serial clock input.
F1
SPI_CS
I
D
SPI Interface - chip select.
D1
SPI_DI
I
D
SPI Interface - serial data input.
E1
SPI_DO
O
D
SPI Interface - serial data output.
A6
SW_B1
I/O
P
Buck Switcher Regulator 1 - Power Switching node, connect to inductor.
B6
SW_B1
I/O
P
Buck Switcher Regulator 1 - Power Switching node, connect to inductor.
F2
SW_B2
I/O
P
Buck Switcher Regulator 2 - Power Switching node, connect to inductor.
G2
SW_B2
I/O
P
Buck Switcher Regulator 2 - Power Switching node, connect to inductor.
H2
SW_B2
I/O
P
Buck Switcher Regulator 2 - Power Switching node, connect to inductor.
F6
SW_B3
I/O
P
Buck Switcher Regulator 3 - Power Switching node, connect to inductor.
G6
SW_B3
I/O
P
Buck Switcher Regulator 3 - Power Switching node, connect to inductor.
H6
SW_B3
I/O
P
Buck Switcher Regulator 3 - Power Switching node, connect to inductor.
B3
VCOMP
I
A
Analog Input for Comparator.
A3
VIN
I
P
Power supply Input Voltage — must be present for device to work; decouple closely to D7.
A5
VIN_B1
I
P
Buck Switcher Regulator 1 - Power supply voltage input for power stage PFET, if Buck 1 is
not used, tie to ground to reduce leakage.
B5
VIN_B1
I
P
Buck Switcher Regulator 1 - Power supply voltage input for power stage PFET, if Buck 1 is
not used, tie to ground to reduce leakage.
(1)
I: Input Pin, O: Output Pin
(2)
A: Analog Pin, D: Digital Pin, G: Ground, P: Power Connection
Copyright © 2013–2014, Texas Instruments Incorporated
5
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