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LM193MW8 データシート(PDF) 3 Page - Texas Instruments

部品番号 LM193MW8
部品情報  Low Power Low Offset Voltage Dual Comparators
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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LM193A, LM193QML
www.ti.com
SNOSAM2C – MAY 2005 – REVISED MARCH 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1)
Supply Voltage, V+
36VDC or ±18VDC
Differential Input Voltage(2)
36V
Input Voltage
−0.3VDC to +36VDC
Input Current (VIN< −0.3VDC)
(3)
50 mA
Maximum Junction Temperature
150°C
Power Dissipation(4)(5)
TO-99
660 mW
CDIP
780 mW
Output Short-Circuit to Ground(6)
Continuous
Operating Temperature Range
−55°C ≤ TA ≤ +125°C
Storage Temperature Range
−65°C ≤ TA ≤ +150°C
Thermal Resistance
θJA
TO-99 (Still Air)
174°C/W
TO-99 (500LF/Min Air flow)
99°C/W
CDIP (Still Air)
146°C/W
CDIP (500LF/Min Air flow)
85°C/W
θJC
TO-99
44°C/W
CDIP
33°C/W
Lead Temperature (Soldering, 10 seconds)
260°C
ESD Tolerance(7)
500V
(1)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2)
Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode
range, the comparator will provide a proper output state. The low input voltage state must not be less than
−0.3V (or 0.3V below the
magnitude of the negative power supply, if used).
(3)
This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of
the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is
also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go
to the V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive
and normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than
−0.3VDC.
(4)
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature),
θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any
temperature is PDmax = (TJmax - TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower.
(5)
The LM193A must be derated based on a 150°C, TJmax. The low bias dissipation and the ON-OFF characteristic of the outputs keep the
chip dissipation very small (PD ≤ 100mV), provided the output transistors are allowed to saturate.
(6)
Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground,
the maximum output current is approximately 20 mA independent of the magnitude of V+.
(7)
Human body model, 1.5K
Ω in series with 100pF.
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Temp°C
1
Static tests at
25
2
Static tests at
125
3
Static tests at
-55
4
Dynamic tests at
25
5
Dynamic tests at
125
6
Dynamic tests at
-55
7
Functional tests at
25
8A
Functional tests at
125
8B
Functional tests at
-55
Copyright © 2005–2013, Texas Instruments Incorporated
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Product Folder Links: LM193A LM193QML


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