データシートサーチシステム |
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LM2506 データシート(PDF) 7 Page - Texas Instruments |
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LM2506 データシート(HTML) 7 Page - Texas Instruments |
7 / 25 page MC MD0 MD1 SER DES LM2506 LM2506 MD1 MC MD0 LM2506 www.ti.com SNLS186B – AUGUST 2006 – REVISED MAY 2013 FUNCTIONAL DESCRIPTION BUS OVERVIEW The LM2506 is a dual link SER/DES configurable part that supports an 18-bit RGB Display interface. The MPL physical layer is purpose-built for an extremely low power and low EMI data transmission while requiring the fewest number of signal lines. No external line components are required, as termination is provided internal to the MPL receiver. A maximum raw throughput of 320 Mbps (raw) is possible with this chipset. When the protocol overhead is taken into account, a maximum data throughput of 240 Mbps is possible. The MPL interface is designed for use with common 50 Ω to 100Ω lines using standard materials and connectors. Lines may be microstrip or stripline construction. Total length of the interconnect is expected to be less than 20cm. Figure 5. MPL Point-to-Point Bus SERIAL BUS TIMING Data valid is relative to both edges for a RGB transaction as shown in Figure 6. Data valid is specified as: Data Valid before Clock, Data Valid after Clock, and Skew between data lines should be less than 500ps. Figure 6. Dual Link Timing (WRITE) SERIAL BUS PHASES There are three bus phases on the MPL serial bus. These are determined by the state of the MC and MD lines. The MPL bus phases are shown in Table 1. The LM2506 supports MPL Level 0 Enhanced Protocol with a Class 0 PHY. Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM2506 |
同様の部品番号 - LM2506 |
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同様の説明 - LM2506 |
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