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SM28VLT32SKGD3 データシート(PDF) 11 Page - Texas Instruments |
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SM28VLT32SKGD3 データシート(HTML) 11 Page - Texas Instruments |
11 / 16 page SM28VLT32-HT www.ti.com SLVSAO2C – NOVEMBER 2012 – REVISED MARCH 2013 APPLICATION INFORMATION The quick status register is intended to be used as feedback of device and command status. The host should evaluate the quick status results at each command execution to determine device status. Additionally, two of the error fields in the quick status are sticky. They will need to be intentionally cleared by the host once detected. The Command and Invalid Data error flags will not self clear. The command error bit indicates that a command failed. This can be either an erase or program command. If this was a program attempt, then the data written may not be valid. The host may decide to re-write this data or pursue some other error recovery path. The Invalid data bit will get set if an attempt to write a bit to a logical 1 (erased state) in a word that has that bit already programmed to a 0. This would likely be the first error seen when writing to an array that contains data. To clear a Command error or Invalid Data error, the host must execute the following SPI command sequence: 1F 00 40 xx. xx is a dummy byte and values are don't care. This SPI command is a special command that is sent to the internal flash controller to clear errors. It is important to note that the quick status capture of the internal setting of the Command error and the Invalid Data flags are delayed by one transaction. Similarly, the Device Busy flag does not get cleared until a second transaction. For example, in the case of polling after a write. If this write generated an Invalid Data error, the sequence would be as follows. SPI WRITE SPI READ DESCRIPTION Write to address 0 with erased value This will cause Invalid Data error if word has 0x17_0000_FFFF 00_xxxx_xxxx been programmed. 0xFF 08 Execute quick status. This result is Device Busy. 0xFF 04 Execute quick status with Invalid Data error. Similarly, if a write or program fails, then the Command error status will show on the second transaction after the failed command. To effectively deal with this in a protocol, the best method is to poll the quick status twice to validate no error occurred. For applications that this method is too costly for SPI bandwidth, the error can be trapped on execution of the following commands with the knowledge that the error belonged to the command 2 transactions earlier. The SPI Frame error and the Read error are errors that return correct status on the next quick status. These two errors are not sticky and only apply to the prior transaction. Provisions for Operating With fCLK Frequencies Less than 12 MHz The SM28VLT32 uses a state machine and registers to implement the correct algorithms for programing, erasure and validation. The register values define counters and loops that determine appropriate setup and hold times, maximum attempts, pulse widths, and other critical parameters. The default values of these registers are defined for fCLK operation in the 10 MHz to 12 MHz range. Operating below 10 MHhz requires changing key registers to properly implement the algorithm. See Table 6 for register settings for specific fCLK ranges. Note, the 10 MHz to 12 MHz values are provided, but are not required to be written as they are the reset defaults. Additionally, the SPI SCLK frequency must be 5/6ths of fCLK or slower for reliable operation. The values below represent the address and value that should be written using the 1D command. Note that first line is a write to F004. This must be first, as it unlocks the test control register and allows modification of the memory mapped registers. Without this write, the contents of the register would not change. It is recommended to follow the register writes with a read to verify that change was properly implemented. The last line is a write back to the test control register to relock it preventing accidental modification of the registers. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: SM28VLT32-HT |
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同様の説明 - SM28VLT32SKGD3 |
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