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SM320C6457CGMHS データシート(PDF) 2 Page - Texas Instruments

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部品番号 SM320C6457CGMHS
部品情報  SM320C6457-HIREL Communications Infrastructure Digital Signal Processor
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ホームページ  http://www.ti.com
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SM320C6457-HIREL
SPRS948 – JULY 2016
www.ti.com
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Product Folder Links: SM320C6457-HIREL
Device Overview
Copyright © 2016, Texas Instruments Incorporated
1.2
Applications
Remote Radio Unit
Software Defined Radio
Voice Processing
Biometrics
1.3
Description
The TMS320C64x+™ DSPs (including the SM320C6457-HIREL device) are the highest-performance
fixed-point DSP generation in the TMS320C6000™ DSP platform. The SM320C6457-HIREL device is
based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW)
architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for applications
including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+
devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.
Based on 65-nm process technology and with performance of up to 9600 million instructions per second
(MIPS) [or 9600 16-bit MMACs per cycle] at a 1.2-GHz clock rate, the SM320C6457-HIREL device offers
cost-effective solutions to high-performance DSP programming challenges. The SM320C6457-HIREL DSP
possesses the operational flexibility of high-speed controllers and the numerical capability of array
processors.
The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier
C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles
the multiply throughput versus the C64x core by performing four 16-bit × 16-bit multiply-accumulates
(MACs) every clock cycle. Thus, eight 16-bit × 16-bit MACs can be executed every cycle on the C64x+
core. At a 1.2-GHz clock rate, this means 9600 16-bit MMACs can occur every second. Moreover, each
multiplier on the C64x+ core can compute one 32-bit × 32-bit MAC or four 8-bit × 8-bit MACs every clock
cycle.
The SM320C6457-HIREL device includes Serial RapidIO®. This high-bandwidth peripheral dramatically
improves system performance and reduces system cost for applications that include multiple DSPs on a
board, such as video and telecom infrastructures and medical/imaging.
The SM320C6457-HIREL DSP integrates a large amount of on-chip memory organized as a two-level
memory system. The level-1 (L1) program and data memories on the SM320C6457-HIREL device are
32KB each. This memory can be configured as mapped RAM, cache, or some combination of the two.
When configured as cache, L1 program (L1P) is a direct mapped cache whereas L1 data (L1D) is a two-
way set associative cache. The level 2 (L2) memory is shared between program and data space and is
2048KB in size. L2 memory can also be configured as mapped RAM, cache, or some combination of the
two. L2 is configurable up to 1MB of cache. The C64x+ Megamodule also has a 32-bit peripheral
configuration (CFG) port, an internal DMA (IDMA) controller, a system component with reset/boot control,
interrupt/exception control, a power-down control, and a free-running 32-bit timer for time stamp.
The peripheral set includes: an inter-integrated circuit bus module (I2C); two multichannel buffered serial
ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode
(ATM) Slave [UTOPIA Slave] port; two 64-bit general-purpose timers (also configurable as four 32-bit
timers); a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose
input/output port (GPIO) with programmable interrupt/event generation modes; an 10/100/1000 Ethernet
media access controller (EMAC), which provides an efficient interface between the SM320C6457-HIREL
DSP core processor and the network; a management data input/output (MDIO) module (also part of the
EMAC) that continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the
system; a glueless external memory interface (64-bit EMIFA), which is capable of interfacing to
synchronous and asynchronous peripherals; and a 32-bit DDR2 SDRAM interface.


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