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SM320C6457CGMHS データシート(PDF) 8 Page - Texas Instruments |
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SM320C6457CGMHS データシート(HTML) 8 Page - Texas Instruments |
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8 / 209 page  8 SM320C6457-HIREL SPRS948 – JULY 2016 www.ti.com Submit Documentation Feedback Product Folder Links: SM320C6457-HIREL Terminal Configuration and Functions Copyright © 2016, Texas Instruments Incorporated 3.2 Pin Attributes Table 3-2 identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and pullup/pulldown resistors, see Section 5.5. Use the symbol definitions in Table 3-1 when reading Table 3-2. Table 3-1. I/O Functional Symbol Definitions FUNCTIONAL SYMBOL DEFINITION Table 3-2 COLUMN HEADING IPD or IPU Internal 100-µA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Section 5.5.6. IPD/IPU A Analog signal Type GND Ground Type I Input terminal Type O Output terminal Type S Supply voltage Type Z Three-state terminal or high impedance Type Table 3-2. Pin Attributes SIGNAL NAME BALL NO. TYPE IPD/IPU DESCRIPTION CLOCK/PLL CONFIGURATIONS CORECLKN AH7 I Clock Input for PLL1 (differential). CORECLKP AH6 I Clock Input for PLL1 (differential). ALTCORECLK AF6 Alternate Core Clock (single-ended) input to main PLL [vs. CORECLK(N|P)]. CORECLKSEL AE6 Core Clock Select. Selects between CORECLK(N|P) and ALTCORECLK to the Main PLL. • When CORECLKSEL = 0, it selects the differential clock [CORECLK(N|P)]. • When CORECLKSEL = 1, it selects the single-ended clock [ALTCORECLK]. SYSCLKOUT AD7 O/Z IPD SYSCLKOUT is the clock output at 1/10 (default rate) of the device speed. DDRREFCLKN E6 I DDR Reference Clock Input to DDR PLL (differential). DDRREFCLKP D6 I DDR Reference Clock Input to DDR PLL (differential). ALTDDRCLK C6 I Alternate DDR Clock (single-ended) input to DDR PLL [vs. DDRREFCLK(N|P)]. DDRCLKSEL G6 I DDR Clock Select. Selects between DDRREFCLK(N|P) and ALTDDRCLK to the DDR PLL. • When DDRCLKSEL = 0, it selects the differential clock [DDRREFCLK(N|P)]. • When DDRCLKSEL = 1, it selects the single-ended clock [ALTDDRCLK]. RIOSGMIICLKN AG6 RapidIO/SGMII Reference Clock to drive the RapidIO and SGMII SerDes (differential). RIOSGMIICLKP AG7 RapidIO/SGMII Reference Clock to drive the RapidIO and SGMII SerDes (differential). JTAG EMULATION TMS Y2 I IPU JTAG test-port mode select TDO AF1 O/Z JTAG test-port data out TDI AB1 I IPU JTAG test-port data in TCK AH3 I IPU JTAG test-port clock TRST AE2 I IPD JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see Section 4.8.19.3.1. |
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同様の説明 - SM320C6457CGMHS |
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