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SM32C6713BGDPM30EP データシート(PDF) 4 Page - Texas Instruments |
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SM32C6713BGDPM30EP データシート(HTML) 4 Page - Texas Instruments |
4 / 133 page SM320C6713-EP SM320C6713B-EP SGUS049K – AUGUST 2003 – REVISED APRIL 2011 www.ti.com List of Figures 4-1 320C67x ™ CPU (DSP Core) Data Paths ..................................................................................... 19 4-2 L2 Memory Configuration ....................................................................................................... 21 4-3 EDMA Channel Parameter Entries (Six Words) for Each EDMA Event .................................................. 25 4-4 CPU (DSP Core) and Peripheral Signals ..................................................................................... 31 4-5 Peripheral Signals ................................................................................................................ 32 4-6 Peripheral Signals ................................................................................................................ 33 4-7 Peripheral Signals ................................................................................................................ 34 4-8 Peripheral Signals ................................................................................................................ 34 5-1 Configuration Example A (Two I2C + Two McASP + GPIO) ............................................................... 42 5-2 Configuration Example B (One I2C + One McBSP + Two McASP + GPIO) ............................................. 43 5-3 Configuration Example C [2 I2C + 1 McBSP + 1 McASP + 1 McASP (DIT) + GPIO] .................................. 44 5-4 Configuration Example D [1 I2C + 2 McBSP + 1 McASP + 1 McASP (DIT) + GPIO + Timers] ....................... 45 5-5 Configuration Example E (1 I2C + HPI + 1 McASP) ......................................................................... 46 5-6 Configuration Example F (One McBSP + HPI + One McASP) ............................................................. 47 6-1 TMS320C6000 ™ DSP Device Nomenclature (Including SM320C6713 and C6713B Devices) ....................... 57 7-1 CPU Control Status Register (CPU CSR) .................................................................................... 59 7-2 Cache Configuration (CCFG) Register ........................................................................................ 61 8-1 PLL and Clock Generator Logic ................................................................................................ 68 9-1 McASP0 and McASP1 Configuration .......................................................................................... 76 9-2 I2Cx Module Block Diagram .................................................................................................... 81 10-1 GPIO Enable (GPEN) Register (Hex Address: 01B0 0000) ............................................................... 82 10-2 GPIO Direction (GPDIR) Register (Hex Address: 01B0 0004) ............................................................ 82 10-3 Power-Down Mode Logic ........................................................................................................ 83 10-4 PWRD Field of the CSR ........................................................................................................ 84 10-5 Schottky Diode Diagram ......................................................................................................... 85 10-6 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 1) (C6713B Only) .................................... 87 10-7 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 0) (C6713B Only) .................................... 88 11-1 Test Load Circuit for AC Timing Measurements ............................................................................. 91 11-2 Input and Output Voltage Reference Levels for AC Timing Measurements .............................................. 91 11-3 Rise and Fall Transition Time Voltage Reference Levels ................................................................... 91 11-4 AC Transient Specification Rise Time ......................................................................................... 92 11-5 AC Transient Specification Fall Time .......................................................................................... 92 11-6 Board-Level Input/Output Timings ............................................................................................. 94 11-7 CLKIN .............................................................................................................................. 94 11-8 CLKOUT2 ......................................................................................................................... 94 11-9 CLKOUT3 ......................................................................................................................... 95 11-10 ECLKIN ............................................................................................................................ 95 11-11 ECLKOUT ......................................................................................................................... 96 11-12 Asynchronous Memory Read ................................................................................................... 99 11-13 Asynchronous Memory Write ................................................................................................... 99 11-14 SBSRAM Read Timing ......................................................................................................... 101 11-15 SBSRAM Write Timing ......................................................................................................... 101 11-16 SDRAM Read Command (CAS Latency 3) ................................................................................. 103 11-17 SDRAM Write Command ...................................................................................................... 103 11-18 SDRAM ACTV Command ..................................................................................................... 104 11-19 SDRAM DCAB Command ..................................................................................................... 104 11-20 SDRAM DEAC Command ..................................................................................................... 105 4 List of Figures Copyright © 2003–2011, Texas Instruments Incorporated |
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