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SM320F28335-EP データシート(PDF) 6 Page - Texas Instruments |
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SM320F28335-EP データシート(HTML) 6 Page - Texas Instruments |
6 / 167 page SM320F28335-EP SPRS581D – JUNE 2009 – REVISED MAY 2012 www.ti.com 6-6 Clock Timing ..................................................................................................................... 110 6-7 Power-on Reset ................................................................................................................. 111 6-8 Warm Reset ..................................................................................................................... 112 6-9 Example of Effect of Writing Into PLLCR Register ......................................................................... 113 6-10 General-Purpose Output Timing .............................................................................................. 114 6-11 Sampling Mode ................................................................................................................. 114 6-12 General-Purpose Input Timing ................................................................................................ 115 6-13 IDLE Entry and Exit Timing .................................................................................................... 116 6-14 STANDBY Entry and Exit Timing Diagram .................................................................................. 117 6-15 HALT Wake-Up Using GPIOn ................................................................................................. 119 6-16 PWM Hi-Z Characteristics ..................................................................................................... 120 6-17 ADCSOCAO or ADCSOCBO Timing ........................................................................................ 122 6-18 External Interrupt Timing ....................................................................................................... 122 6-19 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 125 6-20 SPI Master Mode External Timing (Clock Phase = 1) ..................................................................... 127 6-21 SPI Slave Mode External Timing (Clock Phase = 0) ....................................................................... 129 6-22 SPI Slave Mode External Timing (Clock Phase = 1) ....................................................................... 130 6-23 Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 133 6-24 Example Read Access ......................................................................................................... 135 6-25 Example Write Access ......................................................................................................... 136 6-26 Example Read With Synchronous XREADY Access ...................................................................... 138 6-27 Example Read With Asynchronous XREADY Access ..................................................................... 139 6-28 Write With Synchronous XREADY Access .................................................................................. 141 6-29 Write With Asynchronous XREADY Access ................................................................................ 142 6-30 External Interface Hold Waveform ............................................................................................ 144 6-31 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) .................................................. 145 6-32 ADC Power-Up Control Bit Timing ........................................................................................... 147 6-33 ADC Analog Input Impedance Model ........................................................................................ 148 6-34 Sequential Sampling Mode (Single-Channel) Timing ...................................................................... 149 6-35 Simultaneous Sampling Mode Timing ....................................................................................... 150 6-36 McBSP Receive Timing ........................................................................................................ 154 6-37 McBSP Transmit Timing ....................................................................................................... 154 6-38 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 ................................................... 155 6-39 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 ................................................... 156 6-40 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 ................................................... 156 6-41 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ................................................... 157 6 List of Figures Copyright © 2009–2012, Texas Instruments Incorporated |
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