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SN74ABT3612 データシート(PDF) 8 Page - Texas Instruments |
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SN74ABT3612 データシート(HTML) 8 Page - Texas Instruments |
8 / 34 page SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FIFO write/read operation (continued) Table 3. Port-B Enable Function Table CSB W/RB ENB MBB CLKB B0 – B35 OUTPUTS PORT FUNCTION H X X X X In high-impedance state None L H L X X In high-impedance state None L H H L ↑ In high-impedance state FIFO2 write L H H H ↑ In high-impedance state Mail2 write L L L L X Active, FIFO1 output register None L L H L ↑ Active, FIFO1 output register FIFO1 read L L L H X Active, mail1 register None L L H H ↑ Active, mail1 register Mail1 read (set MBF1 high) synchronized FIFO flags Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously to one another. EFA, AEA, FFA, and AFA are synchronized to CLKA. EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2. Table 4. FIFO1 Flag Operation NUMBER OF WORDS IN FIFO1† SYNCHRONIZED TO CLKB SYNCHRONIZED TO CLKA IN FIFO1† EFB AEB AFA FFA 0 L L H H 1 to X H LH H (X +1) to [64 – (X +1)] H HH H (64 – X) to 63 H HL H 64 H H L L † X is the value in the almost-empty flag and almost-full flag offset register. Table 5. FIFO2 Flag Operation NUMBER OF WORDS IN FIFO2† SYNCHRONIZED TO CLKA SYNCHRONIZED TO CLKB IN FIFO2† EFA AEA AFB FFB 0 L L H H 1 to X H LH H (X +1) to [64 – (X +1)] H HH H (64 – X) to 63 H HL H 64 H H L L † X is the value in the almost-empty flag and almost-full flag offset register. |
同様の部品番号 - SN74ABT3612_15 |
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同様の説明 - SN74ABT3612_15 |
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