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G1-300B-85-2.0 データシート(PDF) 10 Page - National Semiconductor (TI) |
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G1-300B-85-2.0 データシート(HTML) 10 Page - National Semiconductor (TI) |
10 / 247 page www.national.com 10 Revision 1.0 1.0 Architecture Overview The Geode GX1 processor series represents the sixth gen- eration of x86-compatible 32-bit processors with sixth-gen- eration features. The decoupled load/store unit allows reordering of load/store traffic to achieve higher perfor- mance. Other features include single-cycle execution, sin- gle-cycle instruction decode, 16 KB write-back cache, and clock rates up to 300 MHz. These features are made possi- ble by the use of advanced-process technologies and pipe- lining. The GX1 processor has low power consumption at all clock frequencies. Where additional power savings are required, designers can make use of Suspend Mode, Stop Clock capability, and System Management Mode (SMM). The GX1 processor is divided into major functional blocks (as shown in Figure 1-1): • Integer Unit • Floating Point Unit (FPU) • Write-Back Cache Unit • Memory Management Unit (MMU) • Internal Bus Interface Unit • Integrated Functions Instructions are executed in the integer unit and in the float- ing point unit. The cache unit stores the most recently used data and instructions and provides fast access to this infor- mation for the integer and floating point units. Figure 1-1. Internal Block Diagram Write-Back Unit FPU Internal Bus Interface Unit Graphics Memory Display PCI SDRAM Port CS5530 PCI Bus Integer Cache Unit Integrated Functions MMU (CRT/LCD TFT) X-Bus Pipeline Controller Controller Controller C-Bus |
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