データシートサーチシステム |
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SN74AHC74DRE4 データシート(PDF) 2 Page - Texas Instruments |
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SN74AHC74DRE4 データシート(HTML) 2 Page - Texas Instruments |
2 / 27 page SN54AHC74, SN74AHC74 SCLS255K – DECEMBER 1995 – REVISED DECEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Table 1. Function Table (Each Flip-Flop) INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H(1) H(1) H H ↑ H H L H H ↑ L L H H H L X Q0 Q 0 (1) This configuration is unstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. 2 Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: SN54AHC74 SN74AHC74 |
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同様の説明 - SN74AHC74DRE4 |
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