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SN74ACT3632-15PQG4 データシート(PDF) 6 Page - Texas Instruments |
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SN74ACT3632-15PQG4 データシート(HTML) 6 Page - Texas Instruments |
6 / 30 page SN74ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS224D – JUNE 1992 – REVISED APRIL 1998 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL NAME I/O DESCRIPTION ORB O (port B) Output-ready flag. ORB is synchronized to the low-to-high transition of CLKB. When ORB is low, FIFO1 is empty and reads from its memory are disabled. Ready data is present on the output register of FIFO1 when ORB is high. ORB is forced low when FIFO1 is reset and goes high on the third low-to-high transition of CLKB after a word is loaded to empty memory. RST1 I FIFO1 reset. To reset FIFO1, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur while RST1 is low. The low-to-high transition of RST1 latches the status of FS0 and FS1 for AFA and AEB offset selection. FIFO1 must be reset upon power up before data is written to its RAM. RST2 I FIFO2 reset. To reset FIFO2, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur while RST2 is low. The low-to-high transition of RST2 latches the status of FS0 and FS1 for AFB and AEA offset selection. FIFO2 must be reset upon power up before data is written to its RAM. W/RA I Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a low-to-high transition of CLKA. The A0 – A35 outputs are in the high-impedance state when W/RA is high. W/RB I Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for a low-to-high transition of CLKB. The B0 – B35 outputs are in the high-impedance state when W/RB is low. detailed description reset The FIFO memories of the SN74ACT3632 are reset separately by taking their reset (RST1, RST2) inputs low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset inputs can switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pointers and forces the input-ready flag (IRA, IRB) low, the output-ready flag (ORA, ORB) low, the almost-empty flag (AEA, AEB) low, and the almost-full flag (AFA, AFB) high. Resetting a FIFO also forces the mailbox flag (MBF1, MBF2) of the parallel mailbox register high. After a FIFO is reset, its input-ready flag is set high after two clock cycles to begin normal operation. A FIFO must be reset after power up before data is written to its memory. A low-to-high transition on a FIFO reset (RST1, RST2) input latches the value of the flag-select (FS0, FS1) inputs for choosing the almost-full and almost-empty offset programming method. almost-empty flag and almost-full flag offset programming Four registers in the SN74ACT3632 are used to hold the offset values for the AE and AF flags. The port-B almost-empty flag (AEB) offset register is labeled X1 and the port-A almost-empty flag (AEA) offset register is labeled X2. The port-A almost-full flag (AFA) offset register is labeled Y1 and the port-B almost-full flag (AFB) offset register is labeled Y2. The index of each register name corresponds to its FIFO number. The offset registers can be loaded with preset values during the reset of a FIFO or they can be programmed from port A (see Table 1). Table 1. Flag Programming FS1 FS0 RST1 RST2 X1 AND Y1 REGISTERS† X2 AND Y2 REGISTERS‡ H H ↑ X 64 X H H X ↑ X 64 H L ↑ X 16 X H L X ↑ X 16 L H ↑ X 8 X L H X ↑ X 8 L L ↑ ↑ Programmed from port A Programmed from port A † X1 register holds the offset for AEB; Y1 register holds the offset for AFA. ‡ X2 register holds the offset for AEA; Y2 register holds the offset for AFB. |
同様の部品番号 - SN74ACT3632-15PQG4 |
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同様の説明 - SN74ACT3632-15PQG4 |
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