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SN74ACT3632-20PCB データシート(PDF) 9 Page - Texas Instruments

部品番号 SN74ACT3632-20PCB
部品情報  512 횞 36 횞 2CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
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SN74ACT3632-20PCB データシート(HTML) 9 Page - Texas Instruments

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SN74ACT3632
512
× 36 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224D – JUNE 1992 – REVISED APRIL 1998
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
synchronized FIFO flags (continued)
Table 5. FIFO2 Flag Operation
NUMBER OF WORDS
IN FIFO2†‡
SYNCHRONIZED
TO CLKA
SYNCHRONIZED
TO CLKB
IN FIFO2†‡
ORA
AEA
AFB
IRB
0
L
L
H
H
1 to X2
H
LH
H
(X2 + 1) to [512 – (Y2 + 1)]
H
HH
H
(512 – Y2) to 511
H
HL
H
512
H
H
L
L
† X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full
offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset
of FIFO2 or programmed from port A.
‡ When a word loaded to an empty FIFO is shifted to the output register, its
previous FIFO memory location is free.
output-ready flags (ORA, ORB)
The OR flag of a FIFO is synchronized to the port clock that reads data from its array. When the OR flag is high,
new data is present in the FIFO output register. When the OR flag is low, the previous data word is present in
the FIFO output register and attempted FIFO reads are ignored.
A FIFO read pointer is incremented each time a new word is clocked to its output register. From the time a word
is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the OR flag
synchronizing clock; therefore, an OR flag is low if a word in memory is the next data to be sent to the FIFO output
register and three cycles of the port clock that reads data from the FIFO have not elapsed since the time the
word was written. The OR flag of the FIFO remains low until the third low-to-high transition of the synchronizing
clock occurs, simultaneously forcing the OR flag high and shifting the word to the FIFO output register.
A low-to-high transition on an OR flag synchronizing clock begins the first synchronization cycle of a write if the
clock transition occurs at time tsk1, or greater, after the write. Otherwise, the subsequent clock cycle can be the
first synchronization cycle (see Figures 7 and 8).
input-ready flags (IRA, IRB)
The IR flag of a FIFO is synchronized to the port clock that writes data to its array. When the IR flag is high, a
memory location is free in the SRAM to receive new data. No memory locations are free when the IR flag is low
and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, its write pointer is incremented. From the time a word is read from a FIFO,
its previous memory location is ready to be written in a minimum of two cycles of the IR flag synchronizing clock;
therefore, an IR flag is low if less than two cycles of the IR flag synchronizing clock have elapsed since the next
memory write location has been read. The second low-to-high transition on the IR flag synchronizing clock after
the read sets the IR flag high.
A low-to-high transition on an IR flag synchronizing clock begins the first synchronization cycle of a read if the
clock transition occurs at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle can be the
first synchronization cycle (see Figures 9 and 10).


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