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SN74ACT3632-20PQ データシート(PDF) 11 Page - Texas Instruments |
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SN74ACT3632-20PQ データシート(HTML) 11 Page - Texas Instruments |
11 / 30 page SN74ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS224D – JUNE 1992 – REVISED APRIL 1998 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CLKA CLKB RST1 0,1 th(FS) tsu(FS) th(RS) tsu(RS) FS1, FS0 IRA tpd(C-IR) tpd(C-IR) ORB tpd(C-OR) tpd(R-F) tpd(R-F) AEB AFA MBF1 tpd(R-F) Figure 1. FIFO1 Reset Loading X1 and Y1 With a Preset Value of Eight† † FIFO2 is reset in the same manner to load X2 and Y2 with a preset value. AEA Offset (X2) CLKA RST1, RST2 FS1, FS0 0,0 CLKB IRB tpd(C-IR) 4 ENA IRA A0 – A35 th(D) tsu(D) tsu(EN) th(EN) tsk1‡ tsu(FS) th(FS) tpd(C-IR) AFA Offset (Y1) AEB Offset (X1) AFB Offset (Y2) First Word to FIFO1 12 ‡ tsk1 is the minimum time between the rising CLKA edge and a rising CLKB edge for IRB to transition high in the next cycle. If the time between the rising edge of CLKA and rising edge of CLKB is less than tsk1, IRB may transition high one cycle later than shown. NOTE A: CSA = L, W/RA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles. Figure 2. Programming the AF Flag and AE Flag Offset Values After Reset |
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同様の説明 - SN74ACT3632-20PQ |
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