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LM49321 データシート(PDF) 11 Page - Texas Instruments

部品番号 LM49321
部品情報  Audio Sub-System with Stereo DAC, Mono Class AB Loudspeaker Amplifier, OCL/SE Stereo Headphone Output and RF Suppression
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ホームページ  http://www.ti.com
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LM49321 データシート(HTML) 11 Page - Texas Instruments

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ENB
SCK
SDI
TSPISETENB
TSPIHOLDD
TSPISETD
TSPICH
TSPIT
TSPICL
TSPIHOLDENB
Register Address
Data
ENB
SCK
SDI
7
0
7
0
LM49321, LM49321RLEVAL
www.ti.com
SNAS457C – SEPTEMBER 2008 – REVISED MAY 2013
Table 3. PSRR AVDD = 5.0V, fRIPPLE = 217Hz; VRIPPLE = 200mVP-P; CB = 2.2μF; All gains set to 0dB.
MODE
EP (Typ)
LS (Typ)
HP (Typ)
Units
1
68
72
71
dB
2
68
72
71
dB
3
68
72
71
dB
4
68
66
69
dB
5
68
69
70
dB
6
69
72
71
dB
7
68
69
70
dB
Table 4. Dynamic Range and SNR. 3.0V
≤ AVDD ≤ 5.0V. All programmable gain set to 0dB. Units in dB.
DR (Typ)
SNR (Typ)
Units
LS
95
85
dB
HP
95
85
dB
EP
97
85
dB
System Control
The LM49321 is controlled via either a two wire I2C compatible interface or three wire SPI interface, selectable
with the MODE pin. This interface is used to configure the operating mode, interfaces, data converters, mixers
and amplifiers. The LM49321 is controlled by writing 8 bit data into a series of write-only registers, the device is
always a slave for both type of interfaces.
THREE WIRE, SPI INTERFACE (MODE = 1)
Three Wire Mode Write Bus Transaction
Three Wire Mode Write Bus Timing
Figure 4. Three Wire Mode Write Bus
When the part is configured as an SPI device and the enable (ENB) line is lowered the serial data on SDI is
clocked in on the rising edge of the SCK line. The protocol used is 16bit, MSB first. The upper 8 bits (15:8) are
used to select an address within the device, the lower 8 bits (7:0) contain the updated data for this register.
Copyright © 2008–2013, Texas Instruments Incorporated
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Product Folder Links: LM49321 LM49321RLEVAL


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