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SN74V245-15PAGEP データシート(PDF) 5 Page - Texas Instruments |
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SN74V245-15PAGEP データシート(HTML) 5 Page - Texas Instruments |
5 / 42 page SN74V245-EP www.ti.com SCAS932A – DECEMBER 2012 – REVISED JANUARY 2013 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE Supply voltage range, VCC –0.5 V to 5 V Continuous output current, IO (VO = 0 to VCC) ±50 mA Maximum junction temperature, Tj 150°C Storage temperature range, Tstg –65°C to 150°C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (1) MIN TYP MAX UNIT VCC Supply voltage 3 3.3 3.6 V VIH High-level input voltage 2 5 V VIL Low-level input voltage 0.8 V TJ Operating junction temperature –55 125 °C (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. THERMAL INFORMATION SN74V245 THERMAL METRIC(1) PAG UNITS 64 PINS θJA Junction-to-ambient thermal resistance(2) 46.1 θJCtop Junction-to-case (top) thermal resistance(3) 5.8 θJB Junction-to-board thermal resistance(4) 19.7 °C/W ψJT Junction-to-top characterization parameter(5) 0.2 ψJB Junction-to-board characterization parameter(6) 19.4 θJCbot Junction-to-case (bottom) thermal resistance(7) N/A (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: SN74V245-EP |
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