データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

SN74V263-6GGM データシート(PDF) 6 Page - Texas Instruments

部品番号 SN74V263-6GGM
部品情報  3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
Download  52 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI1 - Texas Instruments

SN74V263-6GGM データシート(HTML) 6 Page - Texas Instruments

Back Button SN74V263-6GGM Datasheet HTML 2Page - Texas Instruments SN74V263-6GGM Datasheet HTML 3Page - Texas Instruments SN74V263-6GGM Datasheet HTML 4Page - Texas Instruments SN74V263-6GGM Datasheet HTML 5Page - Texas Instruments SN74V263-6GGM Datasheet HTML 6Page - Texas Instruments SN74V263-6GGM Datasheet HTML 7Page - Texas Instruments SN74V263-6GGM Datasheet HTML 8Page - Texas Instruments SN74V263-6GGM Datasheet HTML 9Page - Texas Instruments SN74V263-6GGM Datasheet HTML 10Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 52 page
background image
SN74V263, SN74V273, SN74V283, SN74V293
8192
× 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Read Clock (RCLK)
Read Enable (REN)
Output Enable (OE)
Empty Flag/Output Ready (EF/OR)
Programmable Almost-Empty Flag (PAE)
Write Clock (WCLK)
SN74V263
SN74V273
SN74V283
SN74V293
Retransmit (RT)
Half-Full Flag (HF)
Interspersed/Noninterspersed Parity (IP)
(
×9 or ×18) Data Out (Q0–Qn)
Big Endian/Little Endian (BE)
Write Enable (WEN)
Load (LD)
(
×9 or ×18) Data In (D0–Dn)
Serial Enable (SEN)
First-Word Fall-Through or Serial Input
(FWFT/SI)
Full Flag/Input Ready (FF/IR)
Programmable Almost-Full Flag (PAF)
Input Width
(IW)
Output Width
(OW)
Partial Reset (PRS)
Master Reset (MRS)
Figure 1. Single-Device-Configuration Signal Flow
description (continued)
A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO
in long-word (
×18) format and read out of the FIFO in small-word (×9) format. If big-endian mode is selected,
the most significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO first, followed
by the least significant byte (LSB). If little-endian format is selected, the LSB of the long word written into the
FIFO is read out first, followed by the MSB. The mode desired is configured during master reset by the state
of the big-endian/little-endian (BE) pin.
The interspersed/noninterspersed parity (IP) bit function allows the user to select the parity bit in the word loaded
into the parallel port (D0–Dn) when programming the flag offsets. If interspersed-parity mode is selected, the
FIFO assumes that the parity bit is located in bit position D8 during the parallel programming of the flag offsets.
If noninterspersed-parity mode is selected, D8 is assumed to be a valid bit and D16 and D17 are ignored. IP
mode is selected during master reset by the state of the IP input pin. This mode is relevant only when the input
width is set to
×18 mode.
The SN74V263, SN74V273, SN74V283, and SN74V293 are fabricated using TI’s high-speed submicron
CMOS technology.
For more information on this device family, see the following application reports:
D Interfacing TI High-Speed External FIFOs With TI DSP Via DSPs’ External Memory Interface (EMIF)
(literature number SPRA534)
D Interfacing TI High-Speed External FIFOs With TI DSP Via DSPs’ Expansion Bus (XBus) (literature number
SPRA547)


同様の部品番号 - SN74V263-6GGM

メーカー部品番号データシート部品情報
logo
Texas Instruments
SN74V263-6GGM TI-SN74V263-6GGM Datasheet
803Kb / 52P
[Old version datasheet]   8192 횞 18, 16384 횞 18, 32768 횞 18, 65536 횞 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
More results

同様の説明 - SN74V263-6GGM

メーカー部品番号データシート部品情報
logo
Texas Instruments
SN74V263-EP TI1-SN74V263-EP Datasheet
702Kb / 49P
[Old version datasheet]   3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74ACT72211L15RJ TI-SN74ACT72211L15RJ Datasheet
305Kb / 21P
[Old version datasheet]   SYNCHRONOUS FIRST-IN FIRST-OUT MEMORIES
SN74ACT72211L TI1-SN74ACT72211L Datasheet
327Kb / 21P
[Old version datasheet]   SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SN74ALVC3631 TI-SN74ALVC3631 Datasheet
448Kb / 28P
[Old version datasheet]   SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SN74ACT7203L TI1-SN74ACT7203L Datasheet
327Kb / 22P
[Old version datasheet]   ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SN74ALVC3631 TI1-SN74ALVC3631_07 Datasheet
476Kb / 29P
[Old version datasheet]   SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
logo
Fairchild Semiconductor
AM3341 FAIRCHILD-AM3341 Datasheet
407Kb / 6P
   64 x 4 BITS FIRST-IN FIRST-OUT MEMORIES
logo
List of Unclassifed Man...
TDC1030 ETC1-TDC1030 Datasheet
226Kb / 14P
   FIRST-IN FIRST-OUT MEMORY
logo
Texas Instruments
SN74V263 TI-SN74V263 Datasheet
803Kb / 52P
[Old version datasheet]   8192 횞 18, 16384 횞 18, 32768 횞 18, 65536 횞 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74ACT7882-20FN TI1-SN74ACT7882-20FN Datasheet
254Kb / 18P
[Old version datasheet]   CLOCKED FIRST-IN, FIRST-OUT MEMORY
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com