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TL16C552FNG4 データシート(PDF) 8 Page - Texas Instruments |
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TL16C552FNG4 データシート(HTML) 8 Page - Texas Instruments |
8 / 33 page TL16C552 DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS102B − DECEMBER 1990 − REVISED MARCH 1996 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 receiver switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figures 9, 10, 11, 12 and 13) PARAMETER TEST CONDITIONS MIN MAX UNIT td9 Delay time from stop to INT high See Note 7 1 RCLK cycle tpd5 Propagation delay time from RCLK high to sample CLK high 100 ns tpd6 Propagation delay time from IOR (RD RBR/RD LSR) high to reset interrupt low CL = 100 pF 150 ns tpd7 Propagation delay time from IOR (RD RBR) low to RXRDY high 150 ns NOTE 7: The receiver data available indication, the overrun error indication, the trigger level interrupts and the active RXRDY indication is delayed three RCLK cycles in the FIFO mode (FCR0 = 1). After the first byte has been received, status indicators (PE, FE, BI) is delayed three RCLK cycles. These indicators are updated immediately for any further bytes received after RD RBR goes active. There are eight RCLK cycle delays for trigger change level interrupts. modem control switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figure 14) PARAMETER TEST CONDITIONS MIN MAX UNIT tpd8 Propagation delay time from IOW (WR MCR) high to RTS (DTR) low/high CL = 100 pF 100 ns tpd9 Propagation delay time from modem input (CTS, DSR) low/high to interrupt high CL = 100 pF 170 ns tpd10 Propagation delay time from IOR (RD MSR) high to interrupt low CL = 100 pF 140 ns tpd11 Propagation delay time from RI high to interrupt high CL = 100 pF 170 ns parallel port timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figure 15) MIN MAX UNIT tsu7 Setup time, data valid before STB low 1 µs th6 Hold time, data valid after STB high 1 µs tw6 Pulse duration, STB low 1 500 µs td10 Delay time, BUSY high to ACK low Defined by printer td11 Delay time, BUSY low to ACK low Defined by printer tw6 Pulse duration, ACK low Defined by printer tw7 Pulse duration, BUSY high Defined by printer td12 Delay time, BUSY high after STB high Defined by printer |
同様の部品番号 - TL16C552FNG4 |
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同様の説明 - TL16C552FNG4 |
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