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TL16C752D データシート(PDF) 3 Page - Texas Instruments |
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TL16C752D データシート(HTML) 3 Page - Texas Instruments |
3 / 56 page 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 RESET DTRB DTRA RTSA OPA RXRDYA INTA INTB A0 A1 A2 NC D5 D6 D7 RXB RXA TXRDYB TXA TXB OPB CSA CSB NC 3 TL16C752D www.ti.com SLLSEN8B – SEPTEMBER 2015 – REVISED MARCH 2016 Product Folder Links: TL16C752D Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated 5 Description (continued) The two UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the UART function is asynchronous communications element (ACE), and these terms are used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that two such devices are incorporated into the TL16C752D device. 6 Pin Configurations and Function PFB Package 48-Pin TQFP Top View N.C. – No internal connection Pin Functions PIN I/O DESCRIPTION NAME TQFP A0 28 I Address bit 0 select. Internal registers address selection. Refer to Figure 26 for register address map. A1 27 I Address bit 1 select. Internal registers address selection. Refer to Figure 26 for register address map. A2 26 I Address bit 2 select. Internal registers address selection. Refer to Figure 26 for register address map. CDA, CDB 40, 16 I Carrier detect (active low). These inputs are associated with individual UART channels A and B. A low on these pins indicates that a carrier has been detected by the modem for that channel. CSA, CSB 10, 11 I Chip select A and B (active low). These pins enable data transfers between the user CPU and the TL16C752D for the channel or channels addressed. Individual UART sections (A and B) are addressed by providing a low on the respective CSA and CSB pin. CTSA, CTSB 38, 23 I Clear to send (active low). These inputs are associated with individual UART channels A and B. A low on the CTS pins indicates the modem or data set is ready to accept transmit data from the TL16C752D device. Status can be checked by reading MSR[4]. These pins only affect the transmit and receive operations when auto CTS function is enabled through the enhanced feature register (EFR[7]), for hardware flow control operation. D0–D4, D5–D7 44 to 48, 1 to 3 I/O Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. DSRA, DSRB 39, 20 I Data set ready (active low). These inputs are associated with individual UART channels A through B. A low on these pins indicates the modem or data set is powered on and is ready for data exchange with the UART. |
同様の部品番号 - TL16C752D |
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同様の説明 - TL16C752D |
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