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TL16C2752FN データシート(PDF) 4 Page - Texas Instruments

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部品番号 TL16C2752FN
部品情報  1.8-V to 5-V DUAL UART WITH 64-BYTE FIFOS
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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TL16C2752FN データシート(HTML) 4 Page - Texas Instruments

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TL16C2752
SLWS188A – JUNE 2006 – REVISED SEPTEMBER 2008 ................................................................................................................................................ www.ti.com
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
FN NO.
RHB NO.
A0
10
3
I
Address 0 select bit. Internal registers address selection.
A1
14
6
I
Address 1 select bit. Internal registers address selection.
A2
15
7
I
Address 2 select bit. Internal registers address selection.
Carrier detect (active low). These inputs are associated with individual UART channels A and
CDA,
42,
B. A low on these pins indicates that a carrier has been detected by the modem for that
I
CDB
30
channel. The state of these inputs is reflected in the modem status register (MSR). These
inputs should be pulled high if unused.
Channel select. UART channel A or B is selected by the state of this pin when CS is a logic 0.
A logic 0 on the CHSEL selects the UART channel B, while a logic 1 selects UART channel A.
CHSEL could just be an address line from the user CPU such as A3. Bit 0 of the alternate
CHSEL
16
8
I
function register (AFR) can temporarily override CHSEL function, allowing the user to write to
both channel register simultaneously with one write cycle when CS is low. It is especially
useful during the initialization routine.
UART chip select (active low). This pin selects channel A or B in accordance with the state of
CS
18
10
I
the CHSEL pin. This allows data to be transferred between the user CPU and the TL16C2752.
Clear to send (active low). These inputs are associated with individual UART channels A and
B. A logic low on the CTS pins indicates the modem or data set is ready to accept transmit
CTSA,
40,
25,
data from the TL16C2752. Status can be tested by reading MSR bit 4. These pins only affect
I
CTSB
28
17
the transmit and receive operations when auto CTS function is enabled through the enhanced
feature register (EFR) bit 7, for hardware flow control operation. These inputs should be pulled
high if unused.
D0–D4
2–6
27–31
Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information
I/O
to or from the controlling CPU. D0 is the least significant bit (LSB) and the first data bit in a
D5–D7
7–9
32, 1, 2
transmit or receive serial data stream.
Data set ready (active low). These inputs are associated with individual UART channels A and
DSRA,
41,
B. A logic low on these pins indicates the modem or data set is powered on and is ready for
I
DSRB
29
data exchange with the UART. The state of these inputs is reflected in the modem status
register (MSR). These inputs should be pulled high if unused.
Data terminal ready (active low). These outputs are associated with individual UART channels
A and B. A logic low on these pins indicates that the TL16C2752 is powered on and ready.
DTRA,
37,
O
These pins can be controlled through the modem control register. Writing a 1 to MCR bit 0
DTRB
27
sets the DTR output to low, enabling the modem. The output of these pins is high after writing
a 0 to MCR bit 0, or after a reset.
GND
12, 22
20
Signal and power ground
Interrupt A and B (active high). These pins provide individual channel interrupts, INTA and
INTB. INTA and INTB are enabled when MCR bit 3 is set to a logic 1, interrupt sources are
INTA,
34,
21,
O
enabled in the interrupt enable register (IER). Interrupt conditions include receiver errors,
INTB
17
9
available receiver buffer data, available transmit buffer space, or when a modem status flag is
detected. INTA and INTB are in the high-impedance state after reset.
Read input (active-low strobe). A high-to-low transition on IOR loads the contents of an
IOR
24
14
I
internal register defined by address bits A0–A2 onto the TL16C2752 data bus (D0–D7) for
access by an external CPU.
Write input (active-low strobe). A low-to-high transition on IOW transfers the contents of the
IOW
20
11
I
data bus (D0–D7) from the external CPU to an internal register that is defined by address bits
A0–A2 and CSA and CSB.
NC
18, 19
No internal connection
Multifunction. This output pin can function as the OP, BAUDOUT, or RXRDY pin. One of these
output signal functions can be selected by the user-programmable bits 1–2 of the alternate
function register (AFR). These signal functions are described as follows:
1.
OP–When OP (active low) is selected, the MF pin is a logic 0 when MCR bit 3 is set to a
logic 1 (see MCR bit 3). MCR bit 3 defaults to a logic 1 condition after a reset or
MFA,
35,
O
powerup.
MFB
19
2.
BAUDOUT–When BAUDOUT function is selected, the 16× baud rate clock output is
available at this pin.
3.
RXRDY–RXRDY (active low) is intended for monitoring DMA data transfers.
If it is not used, leave it unconnected.
4
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Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TL16C2752


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