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TP3401 データシート(PDF) 2 Page - Texas Instruments

部品番号 TP3401
部品情報  DASL Digital Adapter for Subscriber Loops
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI1 - Texas Instruments

TP3401 データシート(HTML) 2 Page - Texas Instruments

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Connection Diagrams
TP3401 DASL
TLH9264 – 2
Order Number TP3401J
See NS Package Number J20A
TP3402 DASL
TLH9264 – 15
Order Number TP3402J
See NS Package Number J20A
TP3403 Package Information
TLH9264 – 16
Order Number TP3403V
See NS Package Number V28A
Pin Descriptions
Name
Description
GND
Negative power supply pin normally 0V All
analog and digital signals are referred to this
pin
VCC
Positive power supply input which must be
a
5Vg5%
MCLK
The 2048 MHz Master Clock input which
(TP3401 only) requires a CMOS logic level clock input from
a stable source Must be synchronous with
BCLK
MCLKXTAL
This pin is the 2048 MHz Master Clock in-
(TP34023403 put which requires either a crystal to be con-
only)
nected between this pin and XTAL2 or a
CMOS logic level clock from a stable source
which must be synchronous with BCLK
XTAL2
This pin is the output side of the oscillator
(TP3402 and
amplifier
TP3403 only)
MBSFSC
In Master Mode this pin is the Master Burst
(TP3401 and
Sync input which may be clocked at 4 kHz
TP3403 only) to synchronize Transmit bursts from a num-
ber of devices at the Master end only The 4
kHz should be nominally a square wave sig-
nal If not used leave this pin open In Slave
mode this pin is a short Frame Sync output
suitable for driving another DASL in Master
Mode to provide a regenerator (ie range-ex-
tender) capability
BCLK
Bit Clock logic signal which determines the
data shift rate for B channel data on the digi-
tal interface side of the device In Master
mode this pin is an input which may be any
multiple
of
8
kHz
from
256
kHz
to
2048 MHz but must be synchronous with
MCLK In Slave mode this pin is an output at
2048 MHz
FSa
In Master mode only this pin is the Transmit
Frame Sync pulse input requiring a positive
edge to indicate the start of the active chan-
nel time for transmit B channel data into Bx
FSa must be synchronous with BCLK and
MCLK In Slave mode only this pin is a digi-
Name
Description
tal output pulse which indicates the 8-bit pe-
riods of the B1 channel data transfer at both
Bx and Br
FSb
In Master mode only this pin is the Receive
Frame Sync pulse input requiring a positive
edge to indicate the start of the active chan-
nel time of the device for receive B channel
data out from Br FSb must be synchronous
with BCLK and MCLK In Slave mode only
this pin is a digital output pulse which indi-
cates the 8-bit periods of the B2 channel
data transfer at both Bx and Br
Bx
Digital input for B1 and B2 channel data to
be transmitted to the line must be synchro-
nous with BCLK
Br
Digital output for B1 and B2 channel data
received from the line
TSr LSD
In Master mode only this pin is an open-
drain output which is normally high imped-
ance but pulls low during both B channel ac-
tive receive time slots In Slave mode only
this pin is an output which is normally high
impedance and pulls low when a valid line
signal is received
Dx
Digital input for D channel data to be trans-
mitted to the line must be synchronous with
DCLK
Dr
Digital output for D channel data received
from the line
DCLKDEN
In Master mode this pin is an input for the
16 kHz serial shift clock for D channel data
on Dx and Dr which should be synchronous
with BCLK It may also be re-configured via
the Control Register to act as an enable in-
put for clocking the D channel interface syn-
chronized to BCLK In Slave mode this is a
16 kHz clock output for D channel data
Crystal specifications 2048 MHz parallel resonant RS s 100X with a
20 pF load Crystal tolerance should be g75 ppm for aging and tempera-
ture
2


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