データシートサーチシステム |
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GS2961A データシート(PDF) 8 Page - Semtech Corporation |
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GS2961A データシート(HTML) 8 Page - Semtech Corporation |
8 / 104 page GS2961A 3Gb/s, HD, SD SDI Integrated Receiver Data Sheet 54385 - 2 September 2012 8 of 104 A5, A6, B5, B6, C5, C6 STAT[0:5] Output MULTI-FUNCTIONAL OUTPUT PORT. Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Each of the STAT [0:5] pins can be configured individually to output one of the following signals: Signal H/HSYNC V/VSYNC F/DE LOCKED Y/1ANC C/2ANC DATA ERROR VIDEO ERROR EDH DETECTED CARRIER DETECT RATE_DET0 RATE_DET1 Default STAT0 STAT1 STAT2 STAT3 STAT4 − STAT5 − − − − − A7, D10, G10, K7 IO_VDD Input Power POWER connection for digital I/O. Connect to 3.3V or 1.8V DC digital. A8 PCLK Output PARALLEL DATA BUS CLOCK Please refer to the Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. 3G 10-bit or 20-bit modePCLK @ 148.5 or 148.5/1.001MHz HD 10-bit modePCLK @ 148.5 or 148.5/1.001MHz HD 20-bit modePCLK @ 74.25 or 74.25/1.001MHz SD 10-bit modePCLK @ 27MHz SD 20-bit modePCLK @ 13.5MHz (Continued) Pin Number Name Timing Type Description |
同様の部品番号 - GS2961A |
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同様の説明 - GS2961A |
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