GS4576C09 datasheet(5/62 Pages) GSI

部品番号	GS4576C09

部品情報	64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM (LLDRAM II)

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メーカー	GSI [GSI Technology]

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GS4576C09/18/36L

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.04 11/2013

5/62

Ball Descriptions

Symbol

Type

Description

A0–A21

Input

Address Inputs—A0–A21 define the row and column addresses for Read and Write Operations. During

a Mode Register Set (MRS), the address inputs define the register settings. They are sampled at the

rising edge of CK.

BA0–B2

Input

Bank Address inputs—Select to which internal bank a command is being applied.

CK, CK

Input

Input Clock—CK and CK are differential input clocks. Addresses and commands are latched on the

rising edge of CK. CK is ideally 180º out of phase with CK.

CS

Input

Chip Select—CS enables the command decoder when Low and disables it when High. When the

command decoder is disabled, new commands are ignored, but internal operations continue.

DQ0–DQ35

Input

Data Input—The DQ signals form the 36-bit data bus. During Read commands, the data is referenced to

both edges of QKx. During Write commands, the data is sampled at both edges of DK.

DK, DK

Input

Input Data Clock—DK and DK are the differential input data clocks. All input data is referenced to both

edges of DK. DK is ideally 180º out of phase with DK. For the x36 device, DQ0– DQ17 are referenced to

DK0 and DK0 and DQ18–DQ35 are referenced to DK1 and DK1. For the x9 and x18 devices, all DQs

are referenced to DK and DK. All DKx and DKx pins must always be supplied to the device.

DM

Input

Input Data Mask—The DM signal is the input mask signal for Write data. Input data is masked when DM

is sampled High. DM is sampled on both edges of DK (DK1 for the x36 configuration). Tie signal to

ground if not used.

TCK

Input

IEEE 1149.1 clock input—This ball must be tied to VSS if the JTAG function is not used.

TMS, TDI

Input

IEEE 1149.1 test inputs—These balls may be left as no connects if the JTAG function is not used.

WE, REF

Input

Command Inputs—Sampled at the positive edge of CK, WE and REF define (together with CS) the

command to be executed.

VREF

Input

Input Reference Voltage—Nominally VDDQ/2. Provides a reference voltage for the input buffers.

ZQ

I/O

External Impedance (25–60

)—This signal is used to tune the device outputs to the system data bus

impedance. DQ output impedance is set to 0.2 * RQ, where RQ is a resistor from this signal to ground.

Connecting ZQ to GND invokes the Minimum Impedance mode. Connecting ZQ to VDD invokes the

Maximum Impedance mode. Refer to the Mode Register Definition diagrams (Mode Register Bit 8 (M8))

to activate or deactivate this function.

QKx, QKx

Output

Output Data Clocks—QKx and QKx are opposite polarity, output data clocks. They are free running,

and during Reads, are edge-aligned with data output from the LLDRAM II. QKx is ideally 180º out of

phase with QKx. For the x36 device, QK0 and QK0 are aligned with DQ0–DQ17, and QK1 and QK1 are

aligned with DQ18–DQ35. For the x18 device, QK0 and QK0 are aligned with DQ0–DQ8, while QK1 and

QK1 are aligned with Q9–Q17. For the x9 device, all DQs are aligned with QK0 and QK0.

同様の部品番号 - GS4576C09

メーカー	部品番号	データシート	部品情報
GSI Technology	GS4576C09GL-18	2Mb / 63P	576Mb CIO Low Latency DRAM (LLDRAM II)
	GS4576C09GL-24	2Mb / 63P	576Mb CIO Low Latency DRAM (LLDRAM II)
	GS4576C09GL-25	2Mb / 63P	576Mb CIO Low Latency DRAM (LLDRAM II)
	GS4576C09GL-33	2Mb / 63P	576Mb CIO Low Latency DRAM (LLDRAM II)
	GS4576C09L-18	2Mb / 63P	576Mb CIO Low Latency DRAM (LLDRAM II)

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