データシートサーチシステム |
|
ST16C1551CJ28 データシート(PDF) 6 Page - Exar Corporation |
|
ST16C1551CJ28 データシート(HTML) 6 Page - Exar Corporation |
6 / 37 page ST16C1550/51 áç áç áç áç 2.97V TO 5.5V UART WITH 16-BYTE FIFO REV. 4.2.0 6 RTS# 22 22 22 22 31 O Request to Send or general purpose output (active low). If this pin is not needed for modem communication, then it can be used as a general I/O. If it is not used, leave it uncon- nected. CTS# 25 25 25 25 34 I Clear to Send or general purpose input (active low). If this pin is not needed for modem communication, then it can be used as a general I/O. If it is not used, connect it to VCC. DTR# 23 23 23 23 32 O Data Terminal Ready or general purpose output (active low). If this pin is not needed for modem communication, then it can be used as a general I/O. If it is not used, leave it unconnected. DSR# 26 26 26 26 39 I Data Set Ready input or general purpose input (active low). If this pin is not needed for modem communication, then it can be used as a general I/O. If it is not used, connect it to VCC. CD# 27 27 27 27 40 I Carrier Detect input or general purpose input (active low). If this pin is not needed for modem communication, then it can be used as a general I/O. If it is not used, connect it to VCC. RI# 17 16 17 16 21 I Ring Indicator input or general purpose input (active low). If this pin is not needed for modem communication, then it can be used as a general I/O. If it is not used, connect it to VCC. ANCILLARY SIGNALS CLK - 12 - 12 - I External Clock Input. This function is associated with 28 pin PDIP and 28 pin PLCC packages only. An external clock must be connected to this pin to clock the baud rate genera- tor and internal circuitry. XTAL1 12 - 12 - 15 I Crystal or external clock input. See Figure 4 for typical oscillator connections. XTAL2 13 - 13 - 16 O Crystal or buffered clock output. See Figure 4 for typical oscillator connections. RESET 24 24 24 24 33 I Reset Input (active high). When it is asserted, the UART configuration registers are reset to default values, see Table 8. RST - 17 - 17 22 O Reset Output (active high). This output is only available on the ST16C1551. When IER bit-5 is a logic 0, RST will follow the logical state of the RESET pin. When IER bit-5 is a logic 1, the user may send software (soft) resets via MCR bit-2. Soft resets from MCR bit-2 are “ORed” with the state of the RESET pin. VCC 28 282828 41 Pwr Power supply input. NAME 28-PIN PDIP (1550) 28-PIN PDIP (1551) 28-PIN PLCC (1550) 28-PIN PLCC (1551) 48-PIN TQFP TYPE DESCRIPTION |
同様の部品番号 - ST16C1551CJ28 |
|
同様の説明 - ST16C1551CJ28 |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |