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AD15700 データシート(PDF) 4 Page - Analog Devices

部品番号 AD15700
部品情報  1 MSPS 16-/14-Bit Analog I/O Port
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD15700 データシート(HTML) 4 Page - Analog Devices

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REV. A
–4–
AD15700
16-BIT ADC TIMING CHARACTERISTICS (–40 C to +85 C, AVDD = DVDD = 5 V, 0VDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
Symbol
Min
Typ
Max
Unit
Refer to Figures 14 and 15
Convert Pulsewidth
t1
5ns
Time between Conversions
t2
1/1.25/1.5
Note 1
ms
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay
t3
30
ns
BUSY HIGH All Modes Except in Master Serial Read after
t4
0.75/1/1.25
ms
Convert Mode (Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
t5
2ns
End of Conversion to BUSY LOW Delay
t6
10
ns
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)
t7
0.75/1/1.25
ms
Acquisition Time
t8
1
ms
RESET Pulsewidth
t9
10
ns
Refer to Figures 16, 17, and 18 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
t10
0.75/1/1.25
ms
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay
t11
20
ns
Bus Access Request to DATA Valid
t12
40
ns
Bus Relinquish Time
t13
515
ns
Refer to Figures 20 and 21 (Master Serial Interface Modes)
2
CS_ADC LOW to SYNC Valid Delay
t14
10
ns
CS_ADC LOW to Internal SCLK Valid Delay
t15
10
ns
CS_ADC LOW to SDOUT Delay
t16
10
ns
CNVST LOW to SYNC Delay (Read During Convert)
t17
25/275/525
ns
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
3
t18
4ns
Internal SCLK Period
3
t19
25
40
ns
Internal SCLK HIGH
3
t20
15
ns
Internal SCLK LOW
3
t21
9ns
SDOUT Valid Setup Time
3
t22
4.5
ns
SDOUT Valid Hold Time
3
t23
2ns
SCLK Last Edge to SYNC Delay
3
t24
3ns
CS_ADC HIGH to SYNC HI-Z
t25
10
ns
CS_ADC HIGH to Internal SCLK HI-Z
t26
10
ns
CS_ADC HIGH to SDOUT HI-Z
t27
10
ns
BUSY HIGH in Master Serial Read after Convert
3
t28
See Table II
ms
CNVST LOW to SYNC Asserted Delay
t29
0.75/1/1.25
ms
Master Serial Read after Convert
SYNC Deasserted to BUSY LOW Delay
t30
25
ns
Refer to Figures 22 and 24 (Slave Serial Interface Modes)
External SCLK Setup Time
t31
5ns
External SCLK Active Edge to SDOUT Delay
t32
316
ns
SDIN Setup Time
t33
5ns
SDIN Hold Time
t34
5ns
External SCLK Period
t35
25
ns
External SCLK HIGH
t36
10
ns
External SCLK LOW
t37
10
ns
NOTES
1In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2In Serial Interface Modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L of 10 pF; otherwise, the load is 60 pF maximum.
3In serial master Read during Convert Mode. See Table II.
Specifications subject to change without notice.


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