MC10EL34, MC100EL34

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6

There are two distinct functional relationships between the Master Reset and Clock:

CASE 1: If the MR is De-asserted (H−L), While the Clock is Still High, the

Outputs will Follow the First Ensuing Clock Rising Edge.

The EN signal will “freeze” the internal divider flip−flops on the first falling edge of CLK after its assertion. The internal

divider flip−flops will maintain their state during the freeze. The EN is deasserted (LOW), and after the next falling edge

of CLK, then the internal divider flip−flops will “unfreeze” and continue to their next state count with proper phase rela-

tionships.

CASE 2: If the MR is De−asserted (H−L), After the Clock has Transitioned Low, the

Outputs will Follow the Second Ensuing Clock Rising Edge.

CASE 1

CASE 2

Figure 2. Timing Diagrams

CLOCK

OUTPUT

MR

CLOCK

OUTPUT

MR

Figure 3. Reset Recovery Time

CLK

Q0

Q1

Q2

EN

Internal Clock

Disabled

Internal Clock

Enabled

MR

CLK

Q0

Q1

Q2

EN

Internal Clock

Disabled

Internal Clock

Enabled

MR