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MC100EP16VT データシート(PDF) 2 Page - ON Semiconductor |
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MC100EP16VT データシート(HTML) 2 Page - ON Semiconductor |
2 / 12 page MC100EP16VT www.onsemi.com 2 1 2 3 45 6 7 8 Q VEE VCC Figure 1. 8-Lead Pinout (Top View) and Logic Diagram D Q D VTT VCTRL 50 W D, D ECL Data Inputs Q, Q ECL Data Outputs VCTRL* Output Swing Control VTT Termination Supply VCC Positive Supply VEE Negative Supply Table 1. PIN DESCRIPTION 50 W * Pin will default LOW when left open. PIN FUNCTION (DFN−8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. EP Table 2. ATTRIBUTES Characteristics Value Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC−8NB TSSOP−8 DFN−8 Level 1 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 140 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. |
同様の部品番号 - MC100EP16VT_16 |
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同様の説明 - MC100EP16VT_16 |
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