MC100LVEL05_16 datasheet(1/6 Pages) ONSEMI

部品番号	MC100LVEL05

部品情報	3.3V ECL 2?륤nput Differential AND/NAND

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July, 2016 − Rev. 5

1

Publication Order Number:

MC100LVEL05/D

MC100LVEL05

3.3 V ECL 2‐Input Differential

AND/NAND

Description

The MC100LVEL05 is a 2-input differential AND/NAND gate. The

device is functionally equivalent to the MC100EL05 device and

operates from a 3.3 V supply voltage. With propagation delays and

output transition times equivalent to the EL05, the LVEL05 is ideally

suited for those applications which require the ultimate in AC

performance at low voltage power supplies.

Because a negative 2-input NAND is equivalent to a 2-input OR

function, the differential inputs and outputs of the device allows the

LVEL05 to also be used as a 2-input differential OR/NOR gate.

Features

• 340 ps Propagation Delay

• High Bandwidth Output Transitions

• ESD Protection:

♦ > 4 kV Human Body Mode

♦ > 200 V Machine Model

• The 100 Series Contains Temperature Compensation

• PECL Mode Operating Range: VCC = 3.0 V to 3.8 V

with VEE = 0 V

• NECL Mode Operating Range: VCC = 0 V

with VEE = −3.0 V to −3.8 V

• Internal Input Pulldown Resistors

• Q Output will Default LOW with All Inputs Open or at VEE

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

• Moisture Sensitivity

♦ Level 1 for SOIC−8

♦ Level 3 for TSSOP−8

♦ For Additional Information, see Application Note AND8003/D

• Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

• Transistor Count = 69 Devices

• These Devices are Pb-Free, Halogen Free and are RoHS Compliant

*For additional marking information, refer to

Application Note AND8002/D.

MARKING DIAGRAMS*

KV05

ALYWG

G

SOIC−8

D SUFFIX

CASE 751

1

8

TSSOP−8

DT SUFFIX

CASE 948R

1

8

1

8

www.onsemi.com

KVL05

ALYW

G

1

8

(Note: Microdot may be in either location)

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

M = Date Code

G = Pb-Free Package

SOIC−8

TSSOP−8

†For information on tape and reel specifications, in-

cluding part orientation and tape sizes, please refer

to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

ORDERING INFORMATION

Device

Package

Shipping†

MC100LVEL05DG

SOIC−8

(Pb-Free)

98 Units/Tube

MC100LVEL05DR2G

SOIC−8

(Pb-Free)

2500/Tape & Reel

TSSOP−8

(Pb-Free)

MC100LVEL05DTR2G

2500/Tape & Reel

TSSOP−8

(Pb-Free)

MC100LVEL05DTG

100 Units/Tube

同様の部品番号 - MC100LVEL05_16

メーカー	部品番号	データシート	部品情報
ON Semiconductor	MC100LVEL05D	140Kb / 8P	3.3V ECL 2-Input Differential AND/NAND December, 2006 ??Rev. 3
	MC100LVEL05D	202Kb / 20P	Evaluation Board Manual for High Frequency SOIC 8 August, 2004 ??Rev. 1
	MC100LVEL05DG	140Kb / 8P	3.3V ECL 2-Input Differential AND/NAND December, 2006 ??Rev. 3
	MC100LVEL05DR2	140Kb / 8P	3.3V ECL 2-Input Differential AND/NAND December, 2006 ??Rev. 3
	MC100LVEL05DR2G	140Kb / 8P	3.3V ECL 2-Input Differential AND/NAND December, 2006 ??Rev. 3

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