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MC100LVEL32DR2G データシート(PDF) 2 Page - ON Semiconductor

部品番号 MC100LVEL32DR2G
部品情報  3.3 V ECL /2 Divider
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メーカー  ONSEMI [ON Semiconductor]
ホームページ  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC100LVEL32DR2G データシート(HTML) 2 Page - ON Semiconductor

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MC100LVEL32
www.onsemi.com
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Figure 1. Logic Diagram and Pinout Assessment
1
2
5
6
7
8
Q
VEE
VCC
Q
CLK
VBB
R
÷2
Reset
CLK
Table 1. PIN DESCRIPTION
Pin
Function
CLK*, CLK**
Q, Q
Reset*
VBB
VCC
VEE
EP
ECL Differential Clock Inputs
ECL Differential Data ÷2 Outputs
ECL Asynch Reset
Reference Voltage Output
Positive Supply
Negative Supply
(DFN8 only) Thermal exposed pad
must be connected to a sufficient ther-
mal conduit. Electrically connect to the
most negative supply (GND) or leave
unconnected, floating open.
*Pin will default low when left open, per internal 75 K pull-down to
VEE.
** Pin will default to VCC/2 when left open per internal 75 KW pull-
down to VEE and 75 KW pull-up to VCC.
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
8 to 0
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8 to 0
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI ≤ VCC
VI ≥ VEE
6 to 0
−6 to 0
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI ≤ VCC
VI ≥ VEE
6 to 0
−6 to 0
V
Iout
Output Current
Continuous
Surge
50
100
mA
IBB
VBB Sink/Source
±0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction-to-Ambient)
0 lfpm
500 lfpm
SOIC−8 NB
SOIC−8 NB
190
130
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
SOIC−8 NB
41 to 44 ±5%
°C/W
qJA
Thermal Resistance (Junction-to-Ambient)
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
TSSOP−8
41 to 44 ±5%
°C/W
qJA
Thermal Resistance (Junction-to-Ambient)
0 lfpm
500 lfpm
DFN−8
DFN−8
129
84
°C/W
Tsol
Wave Solder (Pb-Free)
< 2 to 3 sec @ 260°C
265
°C
qJC
Thermal Resistance (Junction-to-Case)
(Note 1)
DFN−8
35 to 40
°C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)


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