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MTV018 Revision 4.0 10/21/1999

MTV018

MYSON

TECHNOLOGY

FBKGC - Define the output configuration for FBKG pin. When it is set to "0", the FBKG outputs during the dis-

playing of characters or windows, otherwise, it outputs only during the displaying of characters.

TEST -

= 0

⇒ Normal mode.

= 1

⇒ Test mode, not allowed in applications.

FBKGP - Select the polarity of the output pin FBKG

= 1

⇒Positive polarity FBKG output is selected.

= 0

⇒Negative polarity FBKG output is selected.

The initial value is 1 after power up.

PWMCK - Select the output options to HTONE/PWMCK pin.

= 0

⇒ HTONE option is selected.

= 1

⇒ PWMCK option is selected with 50/50 duty cycle and synchronous with the input HFLB.

The frequency is selected by (VCO1, VCO0) shown as Table 4 on page 12.

The initial value is 0 after power up.

SELVCL - Enable auto detection for horizontal and vertical syncs input edge distorition while the bit is set to

"1". The initial value is 0 after power up.

HSP -

= 1

⇒ Accept positive polarity Hsync input.

= 0

⇒ Accept negative polarity Hsync input.

VSP -

= 1

⇒ Accept positive polarity Vsync input.

= 0

⇒ Accept negative polarity Vsync input.

VCO1, VCO0 - Select the appropriate curve partitions of VCO frequency to voltage based on HFLB input and

horizontal resolution register (HORR).

(i) 12K ohm:

= (0, 0)

⇒ 6MHz < Pixel rate < 12MHz

= (0, 1)

⇒ 12MHz < Pixel rate < 24MHz

= (1, 0)

⇒ 24MHz < Pixel rate < 48MHz

= (1, 1)

⇒ 48MHz < Pixel rate < 96MHz

(ii) 11K ohm:

= (0, 0)

⇒ 6.5MHz < Pixel rate < 13MHz

= (0, 1)

⇒ 13MHz < Pixel rate < 26MHz

= (1, 0)

⇒ 26MHz < Pixel rate < 52MHz

= (1, 1)

⇒ 52MHz < Pixel rate < 96MHz

(iii)10K ohm:

= (0, 0)

⇒ 7MHz < Pixel rate < 14MHz

= (0, 1)

⇒ 14MHz < Pixel rate < 28MHz

= (1, 0)

⇒ 28MHz < Pixel rate < 56MHz

= (1, 1)

⇒ 56MHz < Pixel rate < 96MHz

(iv)9.1K ohm:

= (0, 0)

⇒ 7.5MHz < Pixel rate < 15MHz

= (0, 1)

⇒

15MHz < Pixel rate < 30MHz

= (1, 0)

⇒

30MHz < Pixel rate < 60MHz

= (1, 1)

⇒

60MHz < Pixel rate < 96MHz

(v)8.2K ohm:

= (0, 0)

⇒

8MHz < Pixel rate < 16MHz

= (0, 1)

⇒

16MHz < Pixel rate < 32MHz

Column 18

B7

b6

b5

b4

b3

b2

b1

b0

TEST

FBKGP

PWMCK

SELVCL

HSP

VSP

VCO1

VCO0