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8V79S680 データシート(PDF) 9 Page - Integrated Device Technology |
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8V79S680 データシート(HTML) 9 Page - Integrated Device Technology |
9 / 52 page 9 ©2016 Integrated Device Technology, Inc August 4, 2016 8V79S680 Datasheet QCLK to SYSREF Phase Alignment To achieve an output phase alignment between the QCLK_y clock and the QREF_r SYSREF outputs, the CLK and REF input signals must be phase aligned or have a known, deterministic phase relationship. Figure 4 shows an example output phase alignment for aligned clock and SYREF inputs. The closest (smallest phase error) output alignment is achieved by setting the clock phase delay register QCLK_Y to 0x00 (clock) and the SYSREF phase delay register QCLK_Y to 0x04. With a SYSREF phase delay setting of 0x03 or less, the QREF_r output phase is in advance of the QCLK_y phase, which is applicable in JESD204B application. Phase delay settings and propagation delays are independent on the clock and SYSREF frequencies. Table 6 shows recommended phase delay setting several device configurations. Figure 4: QCLK to QREF Phase Alignment Table 6: Recommended Delay Settings for Closest Clock-SYSREF Output Phase Alignmenta a. QCLK and QREF outputs are aligned on the incident edge. Divider Configuration CLK_y REF_r N = ÷1 0x00 0x04 CLK 983.04MHz REF 7.68MHz QCLK_y QCLK_y = 0x00 QREF_r REF_r = 0x04 QCLK_y QCLK_y = 0x00 QREF_r REF_r = 0x03 QREF_r REF_r = 0x02 1017 ps tPD ~ 550ps Input Phase Alignment Output Phase Alignment QREF_r in advance of QCLK_y 131ps 262ps tPD ~ 900ps + (4·131)ps |
同様の部品番号 - 8V79S680 |
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同様の説明 - 8V79S680 |
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