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CAM35C44 データシート(PDF) 7 Page - SMSC Corporation |
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CAM35C44 データシート(HTML) 7 Page - SMSC Corporation |
7 / 50 page 7 NAME TOTAL PINS SYMBOL BUFFER TYPE DESCRIPTION Address Enable 1 AEN I The active high Address Enable pin indicates DMA operations on the host data bus. AEN must be inactive to access the CAM35C44 registers and active during DMA operations regardless of the selected host interface type. ISA I/O Channel Ready 1 IOCHRDY OD12 IOCHRDY is pulled low to extend ISA I/O read/write commands. Only SCE-driven functions in the IrCC 2.0 can be enabled to use IOCHRDY. Multiplex Mode Address Strobe 1 ASTRB I ASTRB is used to internally latch I/O addresses during read/write cycles when a multiplexed address/data host interface type is selected (TABLE 3). No Wait State 1 nNOWS OD12 nNOWS can be enabled to be activated by IrCC 2.0 SCE-driven functions to indicate that an access cycle shorter than the standard ISA I/O cycle can be executed. ISA Reset Drive 1 RESET_DRV IS The RESET_DRV pin is active high and is used to reset the CAM35C44 as described in the appropriate sections in this document. The configuration registers are not affected by this pin except where noted (TABLE 13). The RESET_DRV pin must be valid for 500ns minimum. IRQ 1 IRQ OD12 The IRQ pin is forced active when an interrupt is asserted. IRQ goes inactive as soon as the source of the interrupt has been cleared. The active IRQ pin-state is determined by the IRQ_LEV bit in CR00 (see page 22). |
同様の部品番号 - CAM35C44 |
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同様の説明 - CAM35C44 |
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