74LVC06ADTR2G datasheet(2/7 Pages) ONSEMI

部品番号	74LVC06ADTR2G

部品情報	Low-Voltage CMOS Hex Inverter

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2 / 7 page

74LVC06A

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2

O0

1

A0

4

O1

3

A1

6

O2

5

A2

12

O3

13

A3

10

O4

11

A4

8

O5

9

A5

Figure 2. Logic Diagram

*

* OD

Table 1. PIN NAMES

Pins

Function

An

On

Data Inputs

Outputs

Table 2. TRUTH TABLE

An

On

L

H

Z

L

MAXIMUM RATINGS

Symbol

Parameter

Value

Condition

Unit

VCC

DC Supply Voltage

−0.5 to +6.5

V

VI

DC Input Voltage

−0.5

≤ VI ≤ +6.5

V

VO

DC Output Voltage

−0.5

≤ VO ≤ +6.5

Output in 3−State

V

−0.5

≤ VO ≤ VCC + 0.5

Output in HIGH or LOW State (Note 1)

IIK

DC Input Diode Current

−50

VI < GND

mA

IOK

DC Output Diode Current

−50

VO < GND

mA

+50

VO > VCC

mA

IO

DC Output Source/Sink Current

±50

mA

ICC

DC Supply Current Per Supply Pin

±100

mA

IGND

DC Ground Current Per Ground Pin

±100

mA

TSTG

Storage Temperature Range

−65 to +150

°C

TL

Lead Temperature, 1 mm from Case for

10 Seconds

TL = 260

°C

TJ

Junction Temperature Under Bias

TJ = 135

°C

qJA

Thermal Resistance (Note 2)

SOIC = 85

TSSOP = 100

°C/W

MSL

Moisture Sensitivity

Level 1

ILATCHUP

Latch−up Performance at VCC = 3.6 V

and 125

°C (Note 3)

±250

mA

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. IO absolute maximum rating must be observed.

2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.

3. Tested to EIA/JES078.

ORDERING INFORMATION

Device

Package

Shipping†

74LVC06ADR2G

SOIC−14

(Pb−Free)

2500 / Tape & Reel

74LVC06ADTR2G

TSSOP−14

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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