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9ZXL1251 データシート(PDF) 9 Page - Integrated Device Technology

部品番号 9ZXL1251
部品情報  12-output DB1200ZL Derivative with Integrated 85ohm Terminations
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メーカー  IDT [Integrated Device Technology]
ホームページ  http://www.idt.com
Logo IDT - Integrated Device Technology

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REVISION B 11/20/15
9
12-OUTPUT DB1200ZL DERIVATIVE WITH INTEGRATED 85Ω TERMINATIONS
9ZXL1251 DATASHEET
Electrical Characteristics–Skew and Differential Jitter Parameters
TAMB = TCOM or TIND, unless noted., Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
CLK_IN, DIF[x:0]
tSPO_PLL
Input-to-Output Skew in PLL mode
@100MHz, nominal temperature and voltage
-100
3
100
ps
1,2,4,5,8
CLK_IN, DIF[x:0]
tPD_BYP
Input-to-Output Skew in Bypass mode
@100MHz, nominal temperature and voltage
2.5
3.6
4.5
ns
1,2,3,5,8
CLK_IN, DIF[x:0]
tDSPO_PLL
Input-to-Output Skew Varation in PLL mode
@100MHz, across voltage and temperature
-50
0
50
ps
1,2,3,5,8
Input-to-Output Skew Varation in Bypass mode
@100MHz, across voltage and temperature,
TAMB = TCOM
-250
250
ps
1,2,3,5,8
Input-to-Output Skew Varation in Bypass mode
@100MHz, across voltage and temperature,
TAMB = TIND
-350
350
ps
1,2,3,5,8
Output-to-Output Skew across all outputs
@100MHz, TAMB = TCOM
36
50
ps
1,2,3,8
Output-to-Output Skew across all outputs
@100MHz, TAMB = TIND
38
65
ps
1,2,3,8
PLL Jitter Peaking
jpeak-hibw
LOBW#_BYPASS_HIBW = 1
0
1.2
2.5
dB
7,8
PLL Jitter Peaking
jpeak-lobw
LOBW#_BYPASS_HIBW = 0
0
0.8
2
dB
7,8
PLL Bandwidth
pllHIBW
LOBW#_BYPASS_HIBW = 1
234MHz
8,9
PLL Bandwidth
pllLOBW
LOBW#_BYPASS_HIBW = 0
0.7
1.1
1.4
MHz
8,9
Duty Cycle
tDC
Measured differentially, PLL Mode
45
50
55
%
1
Duty Cycle Distortion
tDCD
Measured differentially, Bypass Mode
@100MHz
-1.5
-0.6
0
%
1,10
PLL mode
25
50
ps
1,11
Additive Jitter in Bypass Mode
1
5
ps
1,11
Notes for preceding table:
6.t is the period of the input clock
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
8. Guaranteed by design and characterization, not 100% tested in production.
9 Measured at 3 db down or half power point.
11 Measured from differential waveform
2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in
bypass mode.
3 All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4 This parameter is deterministic for a given device
5 Measured with scope averaging on to find mean value.
DIF[x:0]
tSKEW_ALL
Jitter, Cycle to cycle
tjcyc-cyc
1 Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
CLK_IN, DIF[x:0]
tDSPO_BYP


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