データシートサーチシステム |
|
9ZXL1930BKLF データシート(PDF) 3 Page - Integrated Device Technology |
|
9ZXL1930BKLF データシート(HTML) 3 Page - Integrated Device Technology |
3 / 18 page 9ZXL1930 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE 3 9ZXL1930 REV D 112015 Pin Descriptions PIN # PIN NAME PIN TYPE DESCRIPTION 1 VDDA PWR 3.3V power for the PLL core. 2 GNDA PWR Ground pin for the PLL core. 3100M_133M# IN 3.3V Input to selec t operating frequenc y See Func tionality Table for Definition 4 HIBW_BYPM_LOBW# IN Trilevel input to select High BW, Bypass or Low BW mode. See PLL Operating Mode Table for Details. 5 CKPWRGD_PD# IN Notifies device to sample latched inputs and s tart up on first high assertion, or exit Power Down Mode on subs equent as sertions. Low enters Power Down Mode. 6 GND PWR Ground pin. 7 VDDR PWR 3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and filtered appropriately. 8 DIF_IN IN 0.7 V Differential TRUE input 9 DIF_IN# IN 0.7 V Differential Complementary Input 10 SMB_A0_tri IN SMBus address bit. This is a tri-level input that work s in conjunction with the SMB_A1 to decode 1 of 9 SMBus Addresses. 11 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant 12 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant 13 SMB_A1_tri IN SMBus address bit. This is a tri-level input that work s in conjunction with the SMB_A0 to decode 1 of 9 SMBus Addresses. 14 FBOUT_NC# OUT Complementary half of differential feedback output. This pin should NOT be connected to anything outside the chip. It exists to provide delay path matching to get 0 propagation delay. 15 FBOUT_NC OUT True half of differential feedback output. This pin should NOT be connected to anything outside the chip. It ex ists to provide delay path matching to get 0 propagation delay. 16 GND PWR Ground pin. 17 DIF_0 OUT 0.7V differential true cloc k output 18 DIF_0# OUT 0.7V differential Complementary clock output 19 DIF_1 OUT 0.7V differential true cloc k output 20 DIF_1# OUT 0.7V differential Complementary clock output 21 VDDIO PWR Power supply for differential outputs 22 GND PWR Ground pin. 23 DIF_2 OUT 0.7V differential true cloc k output 24 DIF_2# OUT 0.7V differential Complementary clock output 25 DIF_3 OUT 0.7V differential true cloc k output 26 DIF_3# OUT 0.7V differential Complementary clock output 27 GND PWR Ground pin. 28 VDD PWR Power supply, nominal 3.3V 29 DIF_4 OUT 0.7V differential true cloc k output 30 DIF_4# OUT 0.7V differential Complementary clock output 31 DIF_5 OUT 0.7V differential true cloc k output 32 DIF_5# OUT 0.7V differential Complementary clock output 33 VDDIO PWR Power supply for differential outputs 34 GND PWR Ground pin. 35 DIF_6 OUT 0.7V differential true cloc k output 36 DIF_6# OUT 0.7V differential Complementary clock output |
同様の部品番号 - 9ZXL1930BKLF |
|
同様の説明 - 9ZXL1930BKLF |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |