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MC14572UBDG データシート(PDF) 1 Page - ON Semiconductor

部品番号 MC14572UBDG
部品情報  Hex Gate
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メーカー  ONSEMI [ON Semiconductor]
ホームページ  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC14572UBDG データシート(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 10
1
Publication Order Number:
MC14572UB/D
MC14572UB
Hex Gate
The MC14572UB hex functional gate is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. These complementary MOS logic gates find
primary use where low power dissipation and/or high noise immunity
is desired. The chip contains four inverters, one NOR gate and one
NAND gate.
Features
Diode Protection on All Inputs
Single Supply Operation
Supply Voltage Range = 3.0 Vdc to 18 Vdc
NOR Input Pin Adjacent to VSS Pin to Simplify Use As An Inverter
NAND Input Pin Adjacent to VDD Pin to Simplify Use As An
Inverter
NOR Output Pin Adjacent to Inverter Input Pin For OR Application
NAND Output Pin Adjacent to Inverter Input Pin For AND
Application
Capable of Driving Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load over the Rated Temperature
Range
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable*
This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
VDD
− 0.5 to +18.0
V
Input or Output Voltage Range
(DC or Transient)
Vin, Vout
− 0.5 to VDD
+ 0.5
V
Input or Output Current (DC or Transient)
per Pin
Iin, Iout
±10
mA
Power Dissipation, per Package (Note 1)
PD
500
mW
Ambient Temperature Range
TA
− 55 to +125
°C
Storage Temperature Range
Tstg
− 65 to +150
°C
Lead Temperature (8−Second Soldering)
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Package: –7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
Device
Package
Shipping
ORDERING INFORMATION
http://onsemi.com
MC14572UBDR2G
SOIC−16
(Pb−Free)
2500/Tape & Reel
MC14572UBDG
SOIC−16
(Pb−Free)
48 Units / Rail
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
MARKING DIAGRAM
SOIC−16
D SUFFIX
CASE 751B
1
16
14572UG
AWLYWW
1
NLV14572UBDR2G* SOIC−16
(Pb−Free)
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
INE
OUTF
IN 1F
IN 2F
VDD
OUTD
IND
OUTE
INB
OUTB
INA
OUTA
VSS
IN 2C
IN 1C
OUTC


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