IDT70T651_15 datasheet(19/28 Pages) IDT

部品番号	IDT70T651

部品情報	HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM

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19

IDT70T651/9S

High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(1,2)

Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1)

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing (M/S = VIH)(1,3,4)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

3. CEX = VIL when CE0X = VIL and CE1X = VIH. CEX = VIH when CE0X = VIH and/or CE1X = VIL.

4. CE0X = OEX = BEnX = VIL. CE1X = VIH.

5632 drw 16

ADDR"A"

and "B"

ADDRESSES MATCH

CE"A"

CE"B"

BUSY"B"

tAPS

tBAC

tBDC

(2)

.

5632 drw 17

ADDR"A"

ADDRESS "N"

ADDR"B"

BUSY"B"

tAPS

tBAA

tBDA

(2)

MATCHING ADDRESS "N"

,

70T651/9S10

Com'l Only

70T651/9S12

Com'l

& Ind

70T651/9S15

Com'l Only

Symbol

Parameter

Min.Max.Min.Max.Min.Max.

Unit

INTERRUPT TIMING

tAS

Address Set-up Time

0

____

0

____

0

____

ns

tWR

Write Recovery Time

0

____

0

____

0

____

ns

tINS

Interrupt Set Time

____

10

____

12

____

15

ns

tINR

Interrupt Reset Time

____

10

____

12

____

15

ns

5632 tbl 16a

NOTES:

1. Timing is the same for both ports.

2. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.

3. 10nsIndustrialspeedgradeisavailableinBF-208andBC-256packagesonly.

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