IDT70T633_12 datasheet(5/27 Pages) IDT

部品番号	IDT70T633

部品情報	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM

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メーカー	IDT [Integrated Device Technology]

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5

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Names

Left Port

Right Port

Names

CE0L,

CE1L

CE0R,

CE1R

Chip Enables (Input)

R/WL

R/WR

Read/Write Enable (Input)

OEL

OER

Output Enable (Input)

A0L - A18L(1)

A0R - A18R(1)

Address (Input)

I/O0L - I/O17L

I/O0R - I/O17R

Data Input/Output

SEML

SEMR

Semaphore Enable (Input)

INTL

INTR

Interrupt Flag (Output)

BUSYL

BUSYR

Busy Flag (Output)

UBL

UBR

Upper Byte Select (Input)

LBL

LBR

Lower Byte Select (Input)

VDDQL

VDDQR

Power (I/O Bus) (3.3V or 2.5V)(2) (Input)

OPTL

OPTR

Option for selecting VDDQX(2,3) (Input)

ZZL

ZZR

Sleep Mode Pin(4) (Input)

M/S

Master or Slave Select (Input)(5)

VDD

Power (2.5V)(2) (Input)

VSS

Ground (0V) (Input)

TDI

Test Data Input

TDO

Test Data Output

TCK

Test Logic Clock (10MHz) (Input)

TMS

Test Mode Select (Input)

TRST

Reset (Initialize TAP Controller) (Input)

5670 tbl 01

NOTES:

1. Address A18x is a NC for IDT70T631.

2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on I/OX.

3. OPTX selects the operating voltage levels for the I/Os and controls on that port.

If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V

levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that

port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied

at 2.5V. The OPT pins are independent of one another—both ports can operate

at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V

with the other at 2.5V.

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when

asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are

not affected during sleep mode. It is recommended that boundry scan not be

operated during sleep mode.

5. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master

(M/S=VIH).

同様の部品番号 - IDT70T633_12

メーカー	部品番号	データシート	部品情報
Integrated Device Techn...	IDT70T633S12BC	342Kb / 27P	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE
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	IDT70T633S12DD	342Kb / 27P	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE

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同様の説明 - IDT70T633_12

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