IDT70T633_12 datasheet(11/27 Pages) IDT

部品番号	IDT70T633

部品情報	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM

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メーカー	IDT [Integrated Device Technology]

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11

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing of Power-Up Power-Down

Waveform of Read Cycles(5)

NOTES:

1. Timing depends on which signal is asserted last, OE, CE, LB or UB.

2. Timing depends on which signal is de-asserted first CE, OE, LB or UB.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tAA, tABE, or tBDD.

5. SEM = VIH.

6. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.

tRC

R/

W

CE

ADDR

tAA

OE

UB, LB

5670 drw 06

(4)

tACE

(4)

tAOE

(4)

tABE

(4)

tOH

(2)

tHZ

(3,4)

tBDD

DATAOUT

BUSYOUT

VALID DATA

(4)

(6)

.

(1)

tLZ/tLZOB

CE

5670 drw 07

tPU

ICC

ISB

tPD

50%

.

同様の部品番号 - IDT70T633_12

メーカー	部品番号	データシート	部品情報
Integrated Device Techn...	IDT70T633S12BC	342Kb / 27P	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE
	IDT70T633S12BCI	342Kb / 27P	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE
	IDT70T633S12BF	342Kb / 27P	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE
	IDT70T633S12BFI	342Kb / 27P	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE
	IDT70T633S12DD	342Kb / 27P	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE

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同様の説明 - IDT70T633_12

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Renesas Technology Corp	70V639	489Kb / 25P	HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM JUNE 2018