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IDT7015S データシート(PDF) 17 Page - Integrated Device Technology

部品番号 IDT7015S
部品情報  HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
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メーカー  IDT [Integrated Device Technology]
ホームページ  http://www.idt.com
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IDT7015S データシート(HTML) 17 Page - Integrated Device Technology

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6.42
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
17
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7015 RAMs.
left port in no way slows the access time of the right port. Both ports are
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,
orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave
anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM
enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol
on-chip power down circuitry that permits the respective port to go into
standbymodewhennotselected. Thisistheconditionwhichisshownin
Truth Table I where CE and SEM are both HIGH.
SystemswhichcanbestusetheIDT7015containmultipleprocessors
or controllers and are typically very HIGH-speed systems which are
softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom
aperformanceincreaseofferedbytheIDT7015'shardwaresemaphores,
whichprovidealockoutmechanismwithoutrequiringcomplexprogram-
ming.
Software handshaking between processors offers the maximum in
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
configurations.TheIDT7015doesnotuseitssemaphoreflagstocontrol
anyresourcesthroughhardware,thusallowingthesystemdesignertotal
flexibilityinsystemarchitecture.
An advantage of using semaphores rather than the more common
methodsofhardwarearbitrationisthatwaitstatesareneverincurredin
either processor. This can prove to be a major advantage in very high-
speedsystems.
How the Semaphore Flags Work
Thesemaphorelogicisasetofeightlatcheswhichareindependent
oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,
fromoneporttotheothertoindicatethatasharedresourceisinuse.The
semaphores provide a hardware assist for a use assignment method
called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore
latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft
processorwantstousethisresource,itrequeststhetokenbysettingthe
latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading
it. If it was successful, it proceeds to assume control over the shared
resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe
rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe
sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest
that semaphore’s status or remove its request for that semaphore to
Busy Logic
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
to prevent the write from proceeding.
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
and use any BUSY indication as an interrupt source to flag the event of
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT7015 RAM in master mode, are push-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
WhenexpandinganIDT7015RAMarrayinwidthwhileusingBUSY
logic, one master part is used to decide which side of the RAM array will
receive a BUSY indication, and to output that indication. Any number of
slavestobeaddressedinthesameaddressrangeasthemasterusethe
BUSYsignalasawriteinhibitsignal.ThusontheIDT7015RAMtheBUSY
pinisanoutputifthepartisusedasamaster(M/Spin=H),andtheBUSY
pinisaninputifthepartusedasaslave(M/Spin=L)asshowninFigure
3.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwiththeR/Wsignal.Failuretoobservethistimingcan
result in a glitched internal write inhibit signal and corrupted data in the
slave.
Semaphores
The IDT7015 are extremely fast Dual-Port 8Kx9 Static RAMs with an
additional8addresslocationsdedicatedtobinarysemaphoreflags.These
flagsalloweitherprocessorontheleftorrightsideoftheDual-PortRAM
toclaimaprivilegeovertheotherprocessorforfunctionsdefinedbythe
systemdesigner’ssoftware.Asanexample,thesemaphorecanbeused
byoneprocessortoinhibittheotherfromaccessingaportionoftheDual-
Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completelyindependentofeachother.Thismeansthattheactivityonthe
2954 drw 19
MASTER
Dual Port
RAM
BUSY (L) BUSY (R)
CE
MASTER
Dual Port
RAM
BUSY (L) BUSY (R)
CE
SLAVE
Dual Port
RAM
BUSY (L) BUSY (R)
CE
SLAVE
Dual Port
RAM
BUSY (L) BUSY (R)
CE
BUSY (L)
BUSY (R)


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