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HD61203U データシート(PDF) 9 Page - Hitachi Semiconductor |
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HD61203U データシート(HTML) 9 Page - Hitachi Semiconductor |
9 / 30 page HD61203U 9 HD61203U Terminal Functions Terminal Name Number of Terminals I/O Connected to Functions V CC GND V EE 1 1 2 Power supply V CC–GND: Power supply for internal logic. V CC–VEE: Power supply for driver circuit logic. V1L, V2L V5L, V6L V1R, V2R V5R, V6R 8 Power supply Liquid crystal display driver level power supply. V1L (V1R), V2L (V2R): Selected level V5L (V5R), V6L (V6R): Non-selected level Voltages of the level power supplies connected to V1L and V1R should be the same. (This applies to the combination of V2L & V2R, V5L & V5R and V6L & V6R respectively.) M/S 1 I V CC or GND Selects master/slave. • M/S = V CC: Master mode When the HD61203U is used with the HD61202U, timing generation circuit operates to supply display timing signals and operation clock to the HD61202U. Each of I/O common terminals DL, DR, CL2, and M is in the output state. • M/S = GND: Slave mode The timing operation circuit stops operating. The HD61203U is used in this mode when combined with the HD61830. Even if combined with the HD61202U, this mode is used when display timing signals (M, data, CL2, etc.) are supplied by another HD61203U in the master mode. Terminals M and CL2 are in the input state. When SHL is V CC, DL is in the input state and DR is in the output state. When SHL is GND, DL is in the output state and DR is in the input state. FCS 1 I V CC or GND Selects shift clock phase. • FCS = V CC Shift register operates at the rising edge of CL2. Select this condition when HD61203U is used with HD61202U or when MA of the HD61830 connects to CL2 in combination with the HD61830. • FCS = GND Shift register operates at the fall of CL2. Select this condition when CL1 of HD61830 connects to CL2 in combination with the HD61830. |
同様の部品番号 - HD61203U |
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同様の説明 - HD61203U |
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