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AD5443YRM-REEL データシート(PDF) 6 Page - Analog Devices

部品番号 AD5443YRM-REEL
部品情報  8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD5443YRM-REEL データシート(HTML) 6 Page - Analog Devices

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REV. 0
–6–
AD5426/AD5432/AD5443
PIN CONFIGURATION
IOUT1 110 RFB
SDIN 56
SYNC
SCLK 47 SDO
GND 38 VDD
IOUT2 29 VREF
AD5426/
AD5432/
AD5443
(Not to Scale)
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1IOUT1
DAC Current Output.
2IOUT2
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
3GND
Ground Pin.
4
SCLK
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial
clock input. Alternatively, by means of the serial control bits, the device may be configured such that data is
clocked into the shift register on the rising edge of SCLK.
5SDIN
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input.
By default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits
allow the user to change the active edge to rising edge.
6
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When
SYNC goes
low, it powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the
shift register on the active edge of the following clocks (power-on default is falling clock edge). In standalone
mode, the serial interface counts clocks and data is latched to the shift register on the 16th active clock edge.
7SDO
Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the
shift register on the falling edge and out via SDO on the rising edge of SCLK. Data will always be clocked
out on the alternate edge to loading data to the shift register. Writing the Readback control word to the
shift register makes the DAC register contents available for readback on the SDO pin, clocked out on the
opposite edges to the active clock edge.
8VDD
Positive Power Supply Input. These parts can be operated from a supply of 3 V to 5.5 V.
9VREF
DAC Reference Voltage Input.
10
RFB
DAC Feedback Resistor pin. Establish voltage output for the DAC by connecting to external amplifier output.


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同様の説明 - AD5443YRM-REEL

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