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TSB43CA42 データシート(PDF) 83 Page - Texas Instruments |
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TSB43CA42 データシート(HTML) 83 Page - Texas Instruments |
83 / 97 page TSB43Cx43A/ TI iceLynx-Micro™ IEEE 1394a-2000 TSB43CA42 Consumer Electronics Solution TEXAS INSTRUMENTS SLLS546F – March 2004 – Revised September 2004 PRODUCTION DATA information is current as of public date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TEXAS INSTRUMENTS Copyright 2004, Texas Instruments Incorporated MARCH 12, 2004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 83 Signal Name Location Direction Description PhyCfgLPS CFR This bit is set in CFR to indicate low power status to the PHY. The ARM must set this when it wants to put the link into lower power mode. The ARM must clear this bit to bring the link out of low power mode. Note: Software must wait at least 2 ms before setting PhyCtrl.LPS after iceLynx-Micro power up. This ensures the internal clocks are stable. InCPUCfg.PhyNoticeEn CFR This bit enables PHY events. These PHY events signal a wake up event to the ARM while the ARM is powered down. The PHY events include LinkOn and PHY_INT. RESET_ARMn InCPUCfg.Reset Pin and CFR Input This pin and CFR bit put ARM into reset. ARM cannot be put into reset by setting InCPUCfg.Reset = 1 if InCPUCfg.ResetDis is set to 1. See the description for InCPUCfg.ResetDis. InCPUCfg.ResetDis bit must be cleared before the ARM is put into reset. The RESET_ARMn pin does not have these qualifying conditions. When RESET_ARMn = low, the ARM is put into reset regardless of InCPUCfg.ResetDis bit status. LINKON PhyCfg.LinkOn Pin and CFR Output This signal is asserted whenever LPS is low and a LinkOn packet is received. It is cleared whenever LPS is detected or the PHY register LCtrl bit is set to zero. PhyCfg.LinkOn gives the current status of the LINKON signal. DISABLE_IFn Pin Input Interface disable. When this pin is asserted by the system, all interfaces on iceLynx-Micro are in high-Z state. This includes Ex- CPU I/F, HSDI I/F, GPIO, and WTCH_DG_TMRn. This function does not include LOW_PWR_RDY. This function is active low. The interface is disabled if DISABLE_IFn=0. InCPUCfg.ResetDis CFR This bit is set by hardware any time one of the following bits transitions from 0 to 1. PhyCfg.LinkOn LinkInt.PhyInt InCPUInt.HPSHi Note: The WTCH_DG_TMRn is configured for output on the Timer2 interrupt. 1.16 16.5K Byte Memory - FIFO 1.16.1 Overview/Description The iceLynx-Micro has 16.5K byte FIFO. The FIFO sizes are set and not programmable. 1.16.2 Isochronous FIFOs 0 and 1 These FIFOs are connected to the HSDI0 and HSDI1 ports, respectively. They are both 4K bytes in size. These FIFOs are designed to handle MPEG2, DSS, DV, or audio data. These data types cannot be interleaved. The buffer must be dedicated to one data type and a single direction. It can be reprogrammed to handle different data types. Both of these buffers can be configured for either transmit or receive. The buffer is only accessible using the HSDI. See Figure 46 for a block diagram of the isochronous FIFO architecture. |
同様の部品番号 - TSB43CA42 |
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同様の説明 - TSB43CA42 |
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