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TSB43CA42 データシート(PDF) 27 Page - Texas Instruments

部品番号 TSB43CA42
部品情報  TI iceLynx-Micro??IEEE 1394a-2000 Consumer Electronics Solution
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ホームページ  http://www.ti.com
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TSB43CA42 データシート(HTML) 27 Page - Texas Instruments

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TSB43Cx43A/
TI iceLynx-Micro™ IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F – March 2004 – Revised September 2004
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
TEXAS
INSTRUMENTS
Copyright
 2004, Texas Instruments Incorporated
MARCH 12, 2004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
1.7
DTCP Encryption – Hardware Implementation (TSB43CA43A and TSB43CA42 Only)
The TSB43CA43A and TSB43CA42 version of iceLynx-Micro is fully compliant with the DTCP method of
digital content protection. iceLynx-Micro supports the baseline M6 cipher, content key creation, and key
updates in iceLynx-Micro hardware. iceLynx-Micro has the capability to encrypt or decrypt MPEG2-DVB,
DSS, DV, or audio. The authentication and key exchange (AKE) is also implemented in hardware.
Customers requiring the DTCP version of iceLynx-Micro must have signed an NDA with Texas
Instruments and be a current DTLA licensee. Information on the DTCP implementation within the
TSB43CA43A and TSB43CA42 devices are found in the following document provided by Texas
Instruments:
Note: Recipients must have signed Texas Instruments NDA and be a current DTLA licensee to receive
this document.
1.8
Program Memory
1.8.1
Overview/Description
The iceLynx-Micro provides 256K bytes of internal program RAM. The program memory is loaded by the
external CPU interface. The external CPU cannot read the program memory.
Anytime the RESET_ARMn pin is asserted (transitions from high to low), the cipher and AKE registers are
cleared.
1.8.2
External CPU (Parallel Mode)
Steps for loading program memory:
1) ARM is placed in reset (using RESET_ARMn pin) and ex-CPU initiates write to the program
memory CFR (Sys.IntMemLoad at 0x5C).If the ARM is only put into reset, there is no change in
the program memory.
2) The program must contain a 2-quadlet header. The 2-quadlet header specifies if the program is
LEB encrypted. See Section 1.9.5 for more information on LEB.
3) The program is loaded into program memory through the Sys.IntMemLoad CFR. The program is
placed in memory starting at address 0x 0000 0000. The ex-CPU indicates the end of program
load by deasserting the RESET_ARMn signal. When the RESET_ARMn signal is deasserted, the
iceLynx-Micro hardware pads the rest of program memory with zeros.
4) The ARM is executing code as soon as RESET_ARMn signal is deasserted and all 256K bytes of
program memory are loaded.
1.9
External CPU Interface
1.9.1
Overview/Description
The ex-CPU accesses iceLynx-Micro configuration registers and FIFOs using 32-bit addressing. The
quadlet-aligned address is provided for the first 16-bit access. The iceLynx-Micro internally increments the
address for the second 16-bit access. All 32 bits of a register or FIFO must be read using back-to-back
transactions. An access to address N must be followed by address N+2.
A 16-bit processor can be used with iceLynx-Micro. However, the processor must access the entire
quadlet address (all 32 bits) in order. For example, for a register address N, the ex-CPU must first access
register address N and then address N+2. It cannot access address N+2 first. If the ex-CPU accesses the
32-bit address incorrectly, the ExCPUInt.ExCPUErr interrupt occurs.
The Ex-CPU can access to iceLynx-Micro by I/O- or memory-type methods. The iceLynx-Micro supports
four memory types of processor interfaces: Type-1, Type-2, I/O Type-1 SH3, and I/O Type-2 M16C. The
ex-CPU I/Fs and access types are categorized as follows:


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