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FM18L08 データシート(PDF) 5 Page - List of Unclassifed Manufacturers

部品番号 FM18L08
部品情報  256Kb 2.7-3.6V Bytewide FRAM Memory
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FM18L08 データシート(HTML) 5 Page - List of Unclassifed Manufacturers

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Ramtron
FM18L08
23 March 2001
5/11
FRAM Design Considerations
When designing with FRAM for the first time, users
of SRAM will recognize a few minor differences. First,
bytewide FRAM memories latch each address on the
falling edge of chip enable. This allows the address
bus to change after starting the memory access. Since
every access latches the memory address on the
falling edge of /CE, users should not ground it as they
might with SRAM.
Users that are modifying existing designs to use
FRAM
should
examine
the
hardware
address
decoders. Decoders should be modified to qualify
addresses with an address valid signal if they do not
already. In many cases, this is the only change
required. Systems that drive chip enable active, then
inactive for each valid address may need no
modifications. An example of the target signal
relationships are shown in Figure 2. Also shown is a
common SRAM signal relationship that will not work
for the FM18L08.
The main design issue is to create a decoder scheme
that will drive /CE active, then inactive for each
address. This accomplishes the two goals of latching
the new address and creating the precharge period.
Figure 2. Memory Address Relationships
Valid Memory Read Relationship
FRAM
Signaling
CE
Address
A1
A2
Data
D1
D2
Invalid Memory Read Relationship
SRAM
Signaling
CE
Address
A1
A2
Data
D1
D2


同様の部品番号 - FM18L08

メーカー部品番号データシート部品情報
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同様の説明 - FM18L08

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