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FM18L08 データシート(PDF) 2 Page - List of Unclassifed Manufacturers

部品番号 FM18L08
部品情報  256Kb 2.7-3.6V Bytewide FRAM Memory
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FM18L08 データシート(HTML) 2 Page - List of Unclassifed Manufacturers

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Ramtron
FM18L08
23 March 2001
2/11
Figure 1. Block Diagram
Address
Latch
A0-A14
CE
Control
Logic
WE
Row
Decoder
Block Decoder
Column Decoder
A0-A7
A8-A9
A10-A14
I/O Latch
Bus Driver
OE
32,768 x 8 FRAM Array
DQ0-7
Pin Description
Pin Name
Pin Number
I/O
Pin Description
A0-A14
1-10, 21, 23-26
I
Address. The 15 address lines select one of 32,768 bytes in the FRAM
array. The address value will be latched on the falling edge of /CE.
DQ0-7
11-13, 15-19
I/O
Data. 8-bit bi-directional data bus for accessing the FRAM array.
/CE
20
I
Chip Enable. /CE selects the device when low. The falling edge of /CE
causes the address to be latched internally. Address changes that
occur after /CE goes low will be ignored until the next falling edge
occurs.
/OE
22
I
Output Enable. When /OE is low the FM18L08 drives the data bus
when valid data is available. Taking /OE high causes the DQ pins to be
tri-stated.
/WE
27
I
Write Enable. Taking /WE low causes the FM18L08 to write the
contents of the data bus to the address location latched by the falling
edge of /CE.
VDD
28
I
Supply Voltage.
VSS
14
I
Ground.
Functional Truth Table
/CE
/WE
/OE
Function
H
X
X
Standby/Precharge
æ
X
X
Latch Address
L
H
L
Read
L
L
X
Write


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